Imagination in push for Java and open source
Imagination Technologies has set up an open-source effort that mirrors ARM’s Linaro group and cut a deal with Oracle for Java optimization.
Tech Design Forum Briefing
Briefing Authors
Paul Dempsey
Paul Dempsey has been a technology journalist for 20 years. His work has also appeared in EETimes, Red Herring and specialist journals published by the Financial Times.
Luke Collins
Luke Collins is a freelance technology journalist with 22 years’ experience. He is a former Editor-in-Chief of Electronics Times in the UK, and co-founded the IP9x series of conferences.
Chris Edwards
Chris Edwards has spent two decades covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology.
Pulsic opts for “layout early, layout often” strategy
Pulsic has developed an automated mixed-signal layout tool that uses multiple generated variants to let designers pick the best implementation.
Verification perspectives 2: formal for the masses and graph-based techniques
The second part of our interview with Mark Olen and Jim Kenney, looks at how formal and graph-based techniques move the market beyond simulation.
Vorsprung durch 3D technik for Audi
The automotive sector could become one of the key markets for 3D integration according to the head of Audi’s progressive semiconductor program.
Multicore fastSpice extends reach
Cadence has expanded the reach of its parallelized fastSpice engine and Spectre XPS tool to support general-purpose analog and mixed-signal designs.
Cadence signs with ARM for core optimizations
Cadence Design Systems has signed up for a licence to ARM cores that will let the EDA supplier optimize support for 32bit and 64bit Cortex processors in its tools.
Cadence ports IP and qualifies tools for 28nm FD-SOI
Cadence Design Systems has developed two sets of IP aimed at the 28nm FD-SOI process developed by STMicroelectronics and qualified tools for the process.
Samsung agrees to make 28nm FD-SOI
STMicroelectronics has found an alternative production partner for the FD-SOI process that the European chipmaker is presenting as an easier option for SoC designers.
Mentor targets 10X cut in reliability test for power electronics
New MicReD power tester identifies failure causes without the need for post-test lab analysis
Synopsys speeds HAPS prototyping with ProtoCompiler
HAPS-specific enhancements to Synplify and Certify join next gen partitioning and planning in suite that claims 3X boost in time-to-prototype