performance analysis


November 3, 2021

Python provides the link for speed checks at Sondrel

Sondrel has combined EDA tools with custom SystemC and Python code to develop a system that can help automate the detailed performance analysis of high-level architectures before RTL is generated.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations: ,
June 23, 2020

Mentor to use UltraSoC acquisition to drive in-life learning

Siemens has agreed to acquire UK-based debug and on-chip instrumentation startup UltraSoC and will fold the operation into Mentor’s Tessent test-software product line.
Article  |  Topics: Blog - IP  |  Tags: , , , , ,   |  Organizations: ,
November 17, 2015

Performance and timeout checks added to on-chip network

Sonics has add static performance analysis to its SonicsStudio tool and timeout detection to its SonicsGN network intended to prevent SoCs locking up.
Article  |  Topics: Blog - IP  |  Tags: , ,   |  Organizations:
December 12, 2012

Altera and ARM unite FPGA and processor debug

Altera has cut a deal with ARM to bring unified debug support to the FPGA fabric and Cortex-A9 processors inside the Cyclone SoC products, using a specialized version of ARM’s DS5 tool.
Article  |  Topics: Blog - Embedded  |  Tags: , , ,   |  Organizations: ,

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