DAC 2012 Notebook

By Paul Dempsey |  No Comments  |  Posted: June 1, 2012
Topics/Categories: Blog Topics, Conferences  |  Tags:

This page will be regularly updated with all Tech Design Forum’s pre-, during and post-DAC coverage. Bookmark or check back from now until the end of the show.

June 7

Synopsys marries virtual and FPGA prototyping: Expose your transaction-level innovations to the real world early on and catch bugs before simulation.

June 6

A look inside Accellera’s UCIS: Accellera has approved version 1.0 of the Unified Coverage Interoperability Standard (UCIS). Here’s how it works.

Intel’s Ivy Bridge chip chop shop: Intel’s Ivy Bridge series of processors were designed from the outset to be split apart and recombined to create variants of the base platform..

June 5

Collaboration key to success at 20nm: Foundries can’t hand down design rules on tablets of stone any more, says GlobalFoundries’ Mojy  Chian.

ARM tips subthreshold power-gating technique: Mike Muller’s DAC keynote included a hint on how to extend supply-gating to very low power circuits.

Rethink tools licensing for cloud computing, EDA Industry told: Could more flexible licensing strategies for cloud-based EDA enable more efficient simulation and a new wave of business models?

Sagantec offers lifebelt to 28nm users, path to 20nm libraries: Can process migration tools help the yield-challenged and speed the path to 20nm?

Avoid IP getting lost in translation: Do you know where your IP has been? Or where it’s going?

June 4

Google your way to DFM: DRC+ is well on its way to becoming an Si2 standard and will enable lithographic yield search engines

Interview: Mentor DFM chief Joe Sawicki on 20nm: Where’s the tool innovation already under way for the incoming node and what does it also mean for users of existing processes.

ESL: are we there yet? It’s been a tough slog getting ESL tools into the market, but Gary Smith says the pace is picking up.

Can FD-SOI shrink chips, solve FinFET issue for SoCs?: The SOI Consortium attempts to counter arguments that finFETs are the way to go.

Blue Pearl partners Xilinx, develops grey-box approach to ARM cores: Blue Pearl is building alliances to bring its timing analysis tools to more users.

June 3

The platforms are taking over: Platform-based design could reshape the IC design business, according to Gary Smith EDA’s Sunday evening talk.

June 1

STMicro, Cadence, GlobalFoundries in 20nm AMS claims: Test chip announced as flows begin to take shape. It’s going to be a busy week.

20(nm) questions: Mentor’s Michael Buehler-Garcia on how the main challenges at 20nm are already being addressed.

May 30

The Gary Smith EDA ‘What to see’ list is live: How to get hold of the analyst’s touchstone guide to the hottest tools at DAC.

Energetic Si2 finds time to look back: Throwing a 10th birthday party for OpenAccess at DAC won’t distract the organization from a near future focused on PDKs, 3D and DFM.

May 29

Atrenta to automate production of power-intent constraints: Updates to existing tools and new ones will help designers get the most bang for their joule.

Introducing Flexras Technologies: French start-up aims to take the pain out of FPGA prototyping with timing-driven partitioning.

Accellera takes first step to a real coverage standard: The Unified Coverage Interoperability Standard will get different vendors tools producing analysis-compatible coverage data. Who said, “And about time, too”?

OCP-IP moves to further ease reuse: The 3.1 specification goes out for review with features such as flexible memory barriers and transaction counting parameters.



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