How high-level synthesis helps optimize low power designs – Part One
Going inside HLS' basics shows how it can deliver power savings over 50% for some applications.
EDA Topics
The requirements for complete RTL signoff
Problems become expensive to fix after the place-and-route stage so it's time to think seriously about the role of RTL signoff within the design flow.
Learn the tricks of the UVM Register Layer
Verify registers without writing code for specific bus interfaces or speed up the loading of configuration registers using the UVM Register Layer. Videos show you how.
Power grid analysis for 2.5D and 3D IC systems
PGA has been IC-centric for mainstream 2D configurations. It must become system-centric for 2.5D and 3D systems.
End mixed-signal infinite loops with electrically aware design
Electrically aware layout tools provide a more efficient alternative to time-consuming rip-up-and-retry practices in mixed-signal nanometer IC design.
Think like designers to fill the SoC verification gap
Build tools around the dataflows and control systems engineers model to address verification challenges posed by burgeoning complexity and low power.
Catching layout-dependent effects on-the-fly
New layout-dependent effects (LDEs) arise at each process node. This methodology updates LDE parameters and uses on-the-fly simulation for early detection.
Accelerating process migration in advanced ASIC design at Bull
How the HPC company used Synopsys' Lynx Design System to standardise its flow and simplify migration to the next node.
A common methodology to manage X propagation in both design and verification
How all types of engineer can focus on X states that represent real risk, and set aside those that are artifacts of a design process.
Managing power intent, signal isolation and level shifting in a UPF-based multi-voltage IC design
Power intent, signal isolation and level shifting can all be controlled in a UPF-based multi-voltage IC design through careful coding.