How high-level synthesis helps optimize low power designs – Part Two
Continuing our series on high-level synthesis (HLS) for low power design. Part Two details how HLS helps you make and evaluate architectural decisions.
EDA Topics
FinFET parasitics come under control
Extracting finFET parasitics means a shift to 3D models, field solvers for greater accuracy, and MCMM techniques.
Debugging with virtual prototypes – Part Two
The second part of our series illustrates VP tools and techniques using the familiar example of Linux bring-up on an ARM-based SoC.
Lithography challenges threaten the cost benefits of IC scaling
The costs of advanced lithography techniques at 1xnm, and the yield and reliability risks from the resultant process variation, will stop many companies getting the typical economic advantages of scaling.
A map of the prototyping ecosystem
Different users within a design team will have varying needs for prototype capabilities. What type of prototype to pick is not always 100 per cent clear. Here are some pointers on how to make the choice.
Goodbye to the mixed-signal black box
In pursuit of better design methodologies coupled with shrinking design-cycles, real-number modeling is emerging as a smart verification choice.
Improving performance through better delay estimation of sub-32nm interconnects
Better delay estimation of sub-32nm interconnects, in which resistivity varies up to 100x between layers, helps Cavium improve overall performance and get ready for even denser processes
Slow winter or new spring for hardware design?
Problems with process scaling make it seem as though the long era of innovative, lucrative hardware design is coming to an end. But is that really the case?
X propagation
X propagation within RTL simulations can hide fatal bugs. Uncovering and eliminating the effect improves design quality and avoids respins.
FPGA-based prototyping to validate the integration of IP into an SoC
A case study describing validation of the integration of USB3.0 and USB2.0 interface IP that illustrates broader challenges FPGA-based prototyping presents.