How high-level synthesis helps optimize low power designs – Part One

By David Pursley, Forte Design Systems |  2 Comments  |  Posted: October 21, 2013
Topics/Categories: EDA - ESL, IC Implementation  |  Tags: ,  | Organizations:

Going inside HLS’ basics shows how it can deliver power savings over 50% for some applications.

Engineers know that the decisions that have most impact on power are those taken early in the design process at the architectural level. They also likely know that high-level synthesis (HLS) allows them to quickly generate hardware from an architectural description. HLS allows engineers to rapidly assess the impact of architectural and algorithmic changes in terms of power, performance, and area at that early stage. However, this is the tip of the iceberg when it comes to exploiting HLS’ qualities for low power design. HLS tools can optimize a design for power in ways that are at best difficult when writing register transfer level (RTL) code by hand. HLS incorporates knowledge of both a design’s specific algorithms and their hardware implementations. As a result, it helps a design team reach many of the best power conclusions when creating the RTL code. Some will enhance the effectiveness of strategies typically used in a low power flow, such as clock gating and multiple threshold voltages. Others, such as those for power-aware sharing and mapping, will further reduce power consumption by changing the microarchitecture altogether. Combined, these optimizations can have a major impact across a broad range of designs. Figure 1 shows some examples.

High-level synthesis power savings on real designs (Source: Forte Design Systems)

Figure 1 High-level synthesis power savings on real designs (Source: Forte Design Systems)

These are all for real commercial designs. They are design- and test vector-dependent, but nevertheless show how HLS delivers very strong results. The following section describes the core HLS flow and how it can be leveraged for low power design. Future articles will dive into more detail on leveraging HLS when creating and optimizing a design for low power. Specifically, they will address the following aspects of low power design with HLS.

  1. Evaluating and optimizing architectural decisions with high-level synthesis
  2. Better leveraging your existing power flow by using high-level synthesis
  3. Further reducing power through high-level synthesis optimizations

The high-level synthesis design flow

From the highest level, high-level synthesis is used to synthesize an algorithmic description into an RTL implementation. In a real production flow, engineers don’t want to create just “an” RTL implementation. Instead, they need an implementation optimized for their architecture and design constraints. Figure 2 shows an abstracted version of the HLS flow and how it takes an untimed architectural description of the system and design constraints to create an optimized, verified RTL implementation. The graphic specifically describes the flow in terms of Cynthesizer from Forte Design Systems, but is essentially generic.

The high-level synthesis flow (Source: Forte Design Systems)

Figure 2 The high-level synthesis flow (Source: Forte Design Systems)

Note that the HLS flow sits on top of the existing RTL flow. It does not replace the RTL flow. It does mean, however, that an engineer spends more time designing and less time writing blocks, sensitivity lists, and finite state machines. It also means that the days of debugging handshakes are over. That though is a discussion for another day. Having HLS on the front-end of the RTL flow entails a few things, but three in particular.

  1. Above all else, the high-level synthesis environment must not take away any of the capabilities in an existing design flow. So, for example, the RTL code produced by HLS needs to be structured in such a way that enabled registers can be inferred as gated clocks, just as they would when writing RTL code by hand.
  2. The HLS tool should primarily address optimizations that generate the best results when put through the low power RTL flow. Staying with the example of clock gating, this means that HLS should focus on maximizing the amount of clock gating while also maximizing the size (fanout) of each gated clock whenever possible.
  3. HLS should focus on optimizations that cannot easily be implemented in the RTL flow. Inversely, HLS should not re-implement optimizations performed in the RTL flow. Again using clock gating as an example, an HLS tool will not synthesize the clock tree and insert integrated clock gating cells and clock buffers. That will be done by other tools later in the flow. Instead, HLS should schedule and implement the design in a way that maximizes the savings in clock tree, register, and combinational power.

Going deeper into high-level synthesis

We have taken an overview of the high-level synthesis flow and described specifically what it offers during power optimization. The second part of this series is also now online and provides a detailed example of how to use HLS to optimize and quantify architectural decisions –– decisions that will have the most impact. Future installments will outline how HLS can increase the value engineers get from their existing low power tools, and discuss optimizations that could only be implemented via HLS.

High-level synthesis resources beyond low power

There is a great deal more to high-level synthesis than its qualities for low power design. For a more general introduction to its strengths and advantages, one good resource is the Forte Design Systems YouTube channel ( The YouTube channel also includes an introduction to the SystemC C++ class library, which allows complex designs to be created and verified at a high-level.

About the author

David Pursley is Director of Product Marketing for Forte Design Systems. He previously held various positions as a field applications engineer, technical marketing engineer, marketing manager, and product line manager in the fields of electronic design automation and embedded computer technology. David would welcome reader’s comments on this and other articles in the high-level synthesis for low power series and on HLS generally. You can contact him at dpursley AT ForteDS DOT com.

Company details

Forte Design Systems Corporate Headquarters Suite 302 100 Century Center Court San Jose CA 95112 USA T: +1 800-800-6494 W:

Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors