Samsung Electronics

GlobalFoundries and Samsung described how they are readying finFETs for production at CPTF 2013 and how the 28nm processes will have a long shelf life.

14nm finFET test-chip designs are moving through Samsung's fab as ARM, Cadence Design Systems and Synopsys continue to check their flows on the new process.

The modelling track at IEDM 2012 showed how germanium could be used in 14nm finFETs. Other work focused on tunnel FETs and analyzing MEMS using Spice.

The advantages and challenges of 3D IC integration, as we add vertical functional integration options to the traditional planar integration brought by the progress of Moore's Law.

Samsung Electronics is setting up a center in Silicon Valley to try to develop technologies that the company hopes will ultimately drive volume for its chipmaking operation.