Work by the Multicore Association to provide a standard way for applications running on different processors to communicate with each other is leading to active implementations.
Cadence Design Systems is nearing completion of a program that will provide a portfolio of documentation for users of its tools who need to obtain safety approvals for their designs.
Ceva has launched the fifth generation of its vision-oriented DSP core family with an architecture tuned for the fast-growing area of convolutional neural networks and deep learning.
Webinar explores the impact of ISO 26262 on DFT requirements, and what is being learnt from the introduction of the standard at ON Semiconductor.
EEMBC has released version 2.0 of its suite for measuring the performance of automotive powertrain tasks on multicore processors.
Cadence Design Systems has added floating-point to its latest core intended for embedded signal processing.
NXP discusses second silicon flavor for automotive radar, after earlier launch of postage-stamp devices.
A new dedicated automotive power tester helps cut simulation errors to just 0.5% with more faithful calibration.
The 53rd Design Automation Conference has published its program for the upcoming event in Austin, Texas, which will include keynotes from AMD, nVidia, and NXP Semiconductors and tracks that connect electronics to biology.
X-Fab Silicon Foundries has upgraded its 6in fab in Lubbock, Texas to handle silicon carbide wafers in parallel with existing silicon production.
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