Synopsys integrates Helic’s EM tools to tighten margins on mixed-signal, analogue and RF SoCs
Better integration of EM modeling and analysis tools with Synopsys’ Custom Compiler should enable tighter design margins
Better integration of EM modeling and analysis tools with Synopsys’ Custom Compiler should enable tighter design margins
Ceva has developed its first processor architecture aimed squarely at deep learning.
Read some edited highlights from the most successful companies in Mentor’s 2017 Technology Leadership Awards.
As geometries have shrunk, layout-dependent effects in CMOS have become ever more problematic. They are not just popping up in performance but reliability and aging effects as one IEDM presentation showed.
A new version of automotive safety standard ISO 26262 is due in 2018 but how close to Level 5 autonomy will it actually take us? And what about security?
IoT kettle maker changed its approach to bolster security, the company’s CTO explained at the IoTSF conference in London.
Altium has rewritten its PCB-design software to improve graphics performance and provide the opportunity to port to non-Windows operating systems such as OS X.
IC Manage is expanding its work on big data in EDA with the creation of a labs program that aims to work with clients on novel ideas for analyzing the gigabytes of output from chip-design tools.
Two-year-old design house make IP choice to use Synopsys DesignWare to build an enterprise SSD controller from scratch.
ST has tweaked its standard HLS flow for ISPs to meet the requirements of ISO 26262