Real Intent CEO Prakash Narain on moving from RTL to SoC sign-off
Prakash Narain of Real Intent on SoC sign-off, static verification, interoperability, predictability, ROI and more.
Tech Design Forum Briefing
Briefing Authors
Paul Dempsey
Paul Dempsey has been a technology journalist for 20 years. His work has also appeared in EETimes, Red Herring and specialist journals published by the Financial Times.
Luke Collins
Luke Collins is a freelance technology journalist with 22 years’ experience. He is a former Editor-in-Chief of Electronics Times in the UK, and co-founded the IP9x series of conferences.
Chris Edwards
Chris Edwards has spent two decades covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology.
Imagination gives WiFi better sync for audio
Imagination Technologies has developed an audio synchonization technology for WiFi networks that the company aims to license to consumer-audio chipmakers and OEMs.
SNUG Boston focuses on challenges of gigascale IC design
Meeting focuses on advanced tools and techniques for the rapid development of gigascale ICs.
ARM buys securable display controller
ARM has agreed to buy from Cadence Design Systems the display controller IP cores developed by recent acquisition Evatronix.
IP providers make plans for the internet of things
ARM and Synopsys both plan to make inroads to the internet of things with their IP strategies.
CDNLive Boston to tackle mixed-signal design, host exhibit
Taking place in Chelmsford, MA on 27 August, the conference will feature user-authored papers, tutorials, a designer expo and keynotes from Cadence and IBM.
Group plans better tools for multicore
A Japanese government-funded project has become the basis of a standard proposed by the Multicore Association that may provide a better way of supporting development for multicore systems.
Three Accellera proposals aim for better TLM
Three companies have donated technology to Accellera designed to improve TLM 2.0 modeling work, focusing on interrupts, register control and memory maps.
Electrically aware Virtuoso aims to head off physical issues
Cadence Design Systems has rolled out a new version of Virtuoso that deals with the physical-implementation issues that arise in the sub-28nm nodes.
Xilinx tapes out for first of 20nm-generation FPGAs
Xilinx aims to be first of the FPGA makers to produce 20nm devices, expecting to move to production samples for some products by the end of the year.