EDA Topics

September 6, 2013

On-chip variation (OCV)

Accounting for on-chip variation (OCV) has become a critical factor in assuring timing closure for nanometer-scale ICs and avoiding over-pessimistic margins.
June 2, 2013

IEEE 1801-2013 (UPF 2.1)

IEEE 1801-2013 updates and refines the Unified Power Format for low-power VLSI design, reflecting changes in power modeling and verification.
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January 23, 2013

Real-value or wreal modelling

Real-valued modelling provides a way of speeding up the simulation of SoCs with significant analog content through the use of discrete-event solvers.
October 3, 2012

System virtual prototyping

The technique enables early software development and hardware/software co-design strategies before a project is more rigidly defined in RTL.
August 21, 2012

2.5D-IC, 3D-IC, and 5.5D-IC – stacked-die integration

A guide to emerging 3D integration techniques for ICs, including a look at various approaches, and some of the tools and standards issues involved.
May 28, 2012


The value of the emulation market has almost doubled in the last four years as the technique becomes increasingly valuable to hardware/software co-verification.
May 23, 2012


VHDL is a hardware description language with rich constructs that can model complex systems. It can also be constrained for use as the starting point of an FPGA or ASIC design.
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April 5, 2012

Assertion-based verification

More than half of design companies claim to use ABV but many have yet to deploy full methodologies.
April 5, 2012

FPGA prototyping

Building a prototype SoC in one or a set of FPGAs can aid field trials, software development and hardware/software integration. But it's not easy, so the decision to go ahead needs careful consideration.
March 28, 2012

Verification IP

Verification IP is becoming an increasingly important component for system design due to the rapid proliferation of new protocols and interfaces, chiefly driven by mobile comms.


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