As part of our nanotechnology focus, we look at the prospects for graphene and carbon nanotubes in electronics. Paul Dempsey reports.
Morris Chang was in on the ground floor of IC innovation at TI and remains there today as chairman of TSMC. Paul Dempsey reports.
Sematech, the leading research consortium for semiconductor manufacturing, has launched a campaign to recruit members from the fabless sector. The move reflects the importance of making manufacturing decisions earlier in the design flow, and is also intended to get input from designers on implementations of such technologies as 3D interconnects, next-generation lithography and novel materials/structures.
Microelectromechanical systems (MEMS) manufacturing continues to be dogged by a technologically and economically inefficient landscape where too many products demand their own bespoke processes and packages. However, the last three years have seen third-party foundries gain more influence over the sector, bringing greater demands for reuse and DFM considerations, earlier in the design flow. The [...]
The demands of manufacturing closure at advanced process nodes make the traditional design-then-fix flow unmanageable. At 28nm and below, designers need a solution that can address manufacturing issues at any point in the design process, enabling a true correct-by-construction methodology. An effective solution must provide design-rule-check and design-for-manufacturing analysis using the actual foundry-approved signoff rules [...]
Product engineering services can be efficiently outsourced and even the biggest players are doing it, says Michel Villemain
This year's Design Automation and Test in Europe conference heard from a broad range of users and suppliers about the challenges to and solutions for getting optimal yields at advanced process nodes, particularly as the industry advances toward 22nm. This article recaps presentations by four executives at the Dresden-hosted event: Pierre Garnier of Texas Instruments, [...]
The time-dependent dielectric breakdown (TDDB) of inter-metal dielectrics on large-scale chips is becoming an increasingly important reliability issue across several semiconductor markets. This mechanism can cause early failures in use and is difficult to detect by traditional test, and hard to control by traditional reliability techniques.
Designers have been using dummy fill to address design for manufacturing for some time, but the process of simply wallpapering shapes into a design's "white space" to help it maintain planarity can no longer cope with the complex challenges presented at today's advanced process nodes. Not only is planarity harder to maintain, but there are [...]
The article offers a case study of the DFM planning and methodology applied during a shrink of Cambridge Silicon Radio's UF6000 system-on-chip from the 130nm to 65nm.
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