May 31, 2011

An Optimized OPC and MDP Flow for Reducing Mask Write Time and Mask Cost

During optical proximity correction (OPC), layout edges or fragments are migrated to proper positions in order to minimize edge placement error (EPE). During this fragment migration, several factors other than EPE are a part of the cost function for optimal fragment displacement. Several factors are devised in favor of OPC stability, which can accommodate room […]

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February 25, 2011

The fundamental question

Nanotechnology's economic potential will only be harnessed through more basic research, according to a new report from the NSF. Paul Dempsey reports.
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February 25, 2011

The waiting game

As part of our nanotechnology focus, we look at the prospects for graphene and carbon nanotubes in electronics. Paul Dempsey reports.
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December 14, 2010

The player

Morris Chang was in on the ground floor of IC innovation at TI and remains there today as chairman of TSMC. Paul Dempsey reports.
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December 14, 2010

Bringing fabless players into manufacturing research

Sematech, the leading research consortium for semiconductor manufacturing, has launched a campaign to recruit members from the fabless sector. The move reflects the importance of making manufacturing decisions earlier in the design flow, and is also intended to get input from designers on implementations of such technologies as 3D interconnects, next-generation lithography and novel materials/structures.
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September 10, 2010

Overcoming manufacturing challenges in MEMS

Microelectromechanical systems (MEMS) manufacturing continues to be dogged by a technologically and economically inefficient landscape where too many products demand their own bespoke processes and packages. However, the last three years have seen third-party foundries gain more influence over the sector, bringing greater demands for reuse and DFM considerations, earlier in the design flow. The [...]
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June 1, 2010

Signoff-driven IC design

The demands of manufacturing closure at advanced process nodes make the traditional design-then-fix flow unmanageable. At 28nm and below, designers need a solution that can address manufacturing issues at any point in the design process, enabling a true correct-by-construction methodology. An effective solution must provide design-rule-check and design-for-manufacturing analysis using the actual foundry-approved signoff rules [...]
June 1, 2010

First fabless, now labless

Product engineering services can be efficiently outsourced and even the biggest players are doing it, says Michel Villemain
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May 1, 2010

Manufacturability and yield toward 22nm

This year's Design Automation and Test in Europe conference heard from a broad range of users and suppliers about the challenges to and solutions for getting optimal yields at advanced process nodes, particularly as the industry advances toward 22nm. This article recaps presentations by four executives at the Dresden-hosted event: Pierre Garnier of Texas Instruments, [...]
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May 1, 2010

Extending critical area analysis to address design for reliability

The time-dependent dielectric breakdown (TDDB) of inter-metal dielectrics on large-scale chips is becoming an increasingly important reliability issue across several semiconductor markets. This mechanism can cause early failures in use and is difficult to detect by traditional test, and hard to control by traditional reliability techniques.
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