Making dummy fill smarter

By Jeff Wilson |  No Comments  |  Posted: May 22, 2012
Topics/Categories: EDA - DFM  |  Tags: ,  | Organizations:

Jeff WilsonJeff Wilson is a DFM product marketing manager in Mentor Graphics' Calibre organization, with responsibility for the development of products that address the challenges of CMP and CAA. He previously worked at Motorola and SCS. Jeff received a BS in Design Engineering from Brigham Young University and an MBA from the University of Oregon.

Dummy fill is the term given to the metal shapes (usually rectangles) placed in an IC design for  manufacturing purposes, rather than to contribute to a logical function. For many years, designers added these dummy shapes because a certain metal density was required to pass the foundry’s density design rule checks (DRC), originally created to improve planarity for manufacturing. The dummy fill process was fairly simple – you defined an area to fill, and your tool filled the area with pre-defined shapes of a specific size and spacing. The two tools commonly used to insert fill were either a physical verification tool like Calibre® nmDRC, or a router.

At today’s advanced nodes, the rules that determine a quality fill result are no longer based on just the minimum and maximum density levels defined by DRC. Density checks now look at density gradient, the density difference between adjacent areas of the layout, and the perimeter of the fill shapes. In addition, manufacturing teams are using fill to address issues associated with rapid thermal annealing (RTA), stress, and etch. Of course, all of these new density requirements must be satisfied without impacting design parameters such as market schedules and timing closure.

While today’s physical verification platforms have geometric analysis tools that can perform the new density and perimeter checks, figuring out how to code those checks and perform the necessary iterations in a complex rule deck requires a concerted effort. On the other hand, although a router knows about the design rules for size and space it is designed to make millions of connections, not balance gradient density or perimeter values across a chip or across layers. Just because you have a hammer doesn’t mean you should use it to tighten a screw.

Analysis-driven fill

To achieve rapid time to market while addressing the growing complexity of fill, designers are looking for a correct-by-construction solution that includes a built-in analysis engine to balance all the new rules and to ensure the fill is created correctly the first time. At the same time, the solution must be easy to use, and avoid creating a significant impact on runtimes or tapeout schedules.

The analysis engine must be able to implement multi-layer fill shapes for both the front end of line (FEOL) base layers, and back end of line (BEOL) metal layers. The FEOL rules include fill shapes that must maintain uniform density relationships across multiple layers to reduce the variability created by RTA and stress. To further reduce the manufacturing stress and provide structural stability, BEOL fill incorporates dummy vias, which must also satisfy multi-layer rules.

Beyond the complexity of the new fill rules, the number of individual fill elements continues to increase dramatically with each new technology. This creates huge GDS files that take longer to transfer and process. One way to deal with this increase is to raise the level of abstraction by moving from individual polygons to a cell-based fill solution, defining a multi-layer pattern of fill shapes that is repeated in many places across the chip. Fill cells are a natural extension of the multi-level fill constructs that must be maintained, and can be used for both FEOL and BEOL. The cell-based approach also provides a benefit in both runtime and file size, which helps maintain the project schedule.

Another design parameter that must be managed is the timing closure loop. The important factors are the ability to support a net-aware fill strategy that protects critical nets by enforcing a user-defined distance from specified nets to any fill shapes. The tool must also back-annotate the fill shapes into the design database to ensure accurate timing verification.

Given the wide variety of EDA tools in use, designers need an effective way to address all of these factors. Selecting a fill solution that supports standard interfaces ensures that designers can easily back-annotate design databases while implementing advanced fill technology. This ability to interact with a variety of toolsets can be critical, given that tools can change from one node to the next. Designers working with tools that use proprietary interfaces to communicate may find themselves caught out when they move to the next node, unable to effectively implement the new required ‘smart’ fill techniques.

As fill requirements become more complex, design teams need smarter tools to handle the challenges of new multi-layer fill constraints and conditions. Fill solutions that combine fill analysis engines with standard interface compatibility and syntax enable designers to implement advanced fill solutions quickly and accurately within existing process flows, even if the design flow changes.

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