Double patterning for sub-28nm ICs

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What is it?

Double patterning is a technique used in the lithographic process that defines the features of integrated circuits at advanced process nodes. It will enable designers to develop chips for manufacture on sub-30nm process nodes using current optical lithography systems. The alternative is to wait for the development of commercially viable steppers using extreme ultraviolet illumination sources, masks and stepper technologies.

The downsides of using double patterning include increased mask (reticle) and lithography costs, and the imposition of further restrictions on the ways in which circuits can be laid out on chip. This affects the complexity of the design process and the performance, variability and density of the resultant devices.

What does double patterning do and why do we need it?

Double patterning counters the effects of diffraction in optical lithography, which happens because the minimum dimensions of advanced process nodes are a fraction of the 193nm wavelength of the illuminating light source. These diffraction effects makes it difficult to produce accurately defined deep sub-micron patterns using existing lighting sources and conventional masks: sharp corners and edges become blurs, and some small features on the mask won’t appear on the wafer at all.

A number of reticle enhancement techniques have been introduced to counteract the diffraction problem as it has become more acute with each new process node.

Phase-shift masks were introduced at the 180nm process node. They alter the phase of the light passing through some areas of the mask, changing the way it is diffracted and so reducing the defocusing effect of mask dimensions that are less than the wavelength of the illuminating light. The downside of using phase-shift techniques is that the masks are more difficult and expensive to make.

Optical-proximity correction (OPC) techniques work out how to distort the patterns on a mask to counter diffraction effects, for example by adding small ‘ears’ to the corners of a square feature on the mask so that they remain sharply defined on the wafer. The technique introduces layout restrictions, has a computational cost in design, and means that it takes longer and costs more to make the corrected masks.

There are useful insights into the way in which different reticle enhancement techniques can interact in this article  about  lithography-friendly design.

There’s a discussion of how to optimise  the parameters of the scripts used to undertake OPC on a full chip design here, and a piece on using a simulated annealing technique to optimise multiple script parameters here. There’s also a discussion of reducing the impact of advanced OPC techniques on mask-making costs, which rise with increasing complexity, here.

Optical equipment improvements, such as lenses with higher numerical apertures that can bend the illuminating light more strongly, and immersion techniques that put layers of liquid between the lens and the wafer to focus the light more strongly, have also helped extend the lifetime of 193nm lithography. The gains available from these techniques have been limited by the lack of significantly superior materials for the lenses and the immersion fluids.

Alternative illumination techniques, such as off-axis illumination and the use of multiple sources, give designers another way to make diffraction and interference effects work to their advantage. The technique introduces complexity to the illumination source in the wafer stepper and to the mask design.

Computational lithography, which blends OPC and alternative illumination by using computation to start with the desired pattern on the wafer and work backwards to define how to pre-distort the mask and configure multiple illumination sources to achieve that pattern on the wafer. This approach takes large amounts of computation power.

There’s a look at how computational lithography has evolved over the past 12 years here, and an interesting discussion of the potential of source-mask optimisation and alternative illumination techniques in a paper here.

Double patterning is another technique used to extend the useful lifetime of 193nm lithography. The process splits dense patterns into two interleaved patterns of less-dense features, defined by two masks. Given sufficiently accurate alignment, the two patterns marry up on the wafer surface to create much denser features than could be achieved with one mask. The primary technique in use at foundries today is based on two complementary masks used in a litho-etch, litho-etch (LELE) process. However, a competing technique, self-aligned double patterning (SADP) can support finer pitches because it does not suffer as badly from misaligned masks.

Where can I use it?

Double patterning will be necessary to define the critical layers of designs being built using 193nm illumination on process nodes below 30nm.

What are the risks of using double patterning?

  • Design restrictions. Double patterning will work best on designs whose critical layers can be split into two separately defined but aligned patterns in a predictable way. This means that producing a design layout that looks like a diffraction grating is good, while a design littered with diagonal lines, jogs, and vias between layers may be less easy to split effectively.
  • Cost. Double patterning is expensive because it uses two masks to define a layer that was defined with one at previous process nodes. This means buying more steppers to maintain a fab’s throughput.
  • Variability. The emphasis on more regular layout with long linear tracks may make designs more susceptible to the performance variability brought on by limited control of the roughness of the edges of patterned .
  • Alignment issues. Double patterning brings alignment issues on to critical layers, rather than between layers as before, with a potential impact on design performance and production yield.

Who is involved in developing double patterning?

Successfully implementing double patterning means drawing on skills and insight from across the semiconductor industry, including IC makers, equipment and materials companies, mask makers, meteorologists, design-tools companies and research organisations. For example, the European LENS project is a consortium of 12 companies working  together to create the technological infrastructure and supply chain for double patterning.


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