Verification

November 21, 2016
Brian Davenport is a staff engineer in Synopsys’ Verification Group focusing on automotive functional safety solutions and technologies.

How functional safety verification helps us build safer cars

Considering the issue of functional safety verification in automotive systems design, within the context of ISO26262
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October 14, 2016
networking-soc-mentor-ixia-featim

Taking risk out of software-driven networking SoCs

How virtualization and integration with hardware testers are enabling networking SoCs in the billion-gate era.
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September 29, 2016
Visual: cars speeding along a road

The challenges of automotive functional safety verification

Engineers developing an SoC for the automotive market have to show that it doesn’t have functional safety issues - even if the SoC enters an unexpected state. Here's how to tackle the safety verification task.
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September 9, 2016
Jean-Marie Brunet is Senior Director of Marketing for the Emulation Division at Mentor Graphics.

The inside track on emulation growth

Analysts say there is a $1B market on the horizon. We talk with Mentor's Jean-Marie Brunet about where such a number could come from.
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August 28, 2016
Chips on a wafer

Addressing the verification challenges of complex SoCs

Three senior verification specialists talk about how they are navigating the challenge of verifying multibillion-transistor SoCs with limited compute resource, increasing coverage demands and shrinking timescales.
July 22, 2016
Dr Lauro Rizzatti, verification consultant

The emulator thrives as verification models mushroom

Emulators have come a long way since their first introduction nearly three decades ago.
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July 15, 2016
Hans van der Schoot is a methodologist in the Emulation division of Mentor Graphics

Team UVM and emulation for testbench acceleration

To verify large, complex designs and meet time-to-market, you must use both simulation and emulation.
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July 5, 2016
Anders Nordstrom, senior corporate applications engineer, Verification Group, Synopsys

Are you formally secure?

A look at how formal verification strategies can be used to check the security feature of complex SoCs for potential data leakage and data integrity issues
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June 1, 2016
How Google and Qualcomm use HLS and HLV

How Google and Qualcomm exploit real world HLS and HLV

By taking a pragmatic approach, the two technology giants have comfortably adopted high-level synthesis and verification - and have shared their experiences.
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May 30, 2016
Anders Nordstrom, senior corporate applications engineer, Verification Group, Synopsys

Comparing your design to itself – a crucial part of verification

Sequential equivalence checking can help trap errors introduced by clock gate insertion, uninitialised registers, and X propagation issues.

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