Verification

June 30, 2015
Mark Handover is an applications engineer with Mentor Graphics

Back to basics – doing formal the right way

Considering design style, assertions, engines and coverage can help ease the development of an effective formal verification test plan
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June 22, 2015
Synopsys MIPI verification featimg

Verifying MIPI interfaces in SoCs

Verifying MIPI interfaces including CSI-2, CPHY, DPHY, MPY, Unipro and the UFS host controller on complex SoCs - should you make or buy the necessary VIP?
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May 31, 2015
realintent-metastable-thm

Technology trends demand netlist-level CDC verification

Complex processes and aggressive synthesis interventions are increasing the risks of metastability, creating a need for netlist-level CDC verification
May 29, 2015
Mentor Graphics/Wilson Research Group Functional Verification Study

Smaller designs face greater risk of respins

Research study suggests the maturity of your verification flow determines the likelihood of first-pass success far more than the complexity inherent in design size.
May 11, 2015
Fast to slow CDC - featimg

Verifying clock domain crossings when using fast-to-slow clocks

A look at three techniques to verify the validity of signals moving between clock domains
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May 6, 2015
Formality featimg

Fixing late ECOs in ARM core subsystems at STMicroelectronics

Using equivalence checking to validate ECOs in ARM core subsystem development at STMicroelectronics
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May 6, 2015
Mike Bartley is CEO of TVS. He has over 25 years' experience of building and managing test and verification teams at STMicroelectronics, Infineon and Elixent/Panasonic. He has consulted on multiple verification projects for companies including ARM and Infineon.

Achieving safety and security in SoC development

Designers will have to update development processes to achieve the rigorous safety certifications required in automotive, rail, avionics and similar markets
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April 30, 2015
Dr Lauro Rizzatti is an independent verification consultant. You can contact him at lauro AT rizzatti DOT com

Putting emulation on the map

Emulation is now served by all three leading vendors and is a hot topic for discussion among engineers. The major verification conferences need to follow suit.
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April 27, 2015
Enabling FPGA prototyping of large ASIC and SoC designs - featimg

Enabling FPGA prototyping of large ASIC and SoC designs

How tool parallelism, automatic partitioning, deep debug memories and time domain multiplexing eases FPGA prototyping of large ASIC and SoC designs
April 20, 2015
Prototyping Imagination GPUs - featimg

Developing and integrating configurable GPU IP using FPGA-based prototyping

How Imagination Technologies used FPGA-based prototyping to develop its GPU IP and integrate it into a real world system
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