The next boost to verification productivity will come from the integration of multiple strategies and tools.
Catching x-propagation issues at RTL saves time and reduces uncertainty in gate-level verification
Increasingly complex state machines are driving the need for smarter ways of reporting errors such as deadlocks and unreachable code in the source RTL.
The number of scenarios needed for MCMM timing analysis has skyrocketed. IC implementation calls for a concurrent approach to deal with the issue.
The fourth installment discusses the extra levels of debug capability available when using virtual prototypes through the example of an ARM big.LITTLE-based embedded system.
Find how to spot some of the most common false clock-domain crossing (CDC) violations and how to efficiently find actual CDC problems that could kill a design if not corrected.
Three key characteristics determine a verification platform's ability to add value to the design flow. But how they score within a project depend on how each is applied and at which point.
This part illustrates the technique using examples addressing memory corruption, multicore systems and cache coherency with particular reference to watchpoints.
Agile development started in the software domain but the methodology shows promise for SoC verification. Formal verification techniques can help implement an Agile flow.
How Marvell used an enhanced ECO tool flow for SoC design to cut overall time-to-timing-closure by nearly 70%.
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