Verification

April 22, 2014
Tech Design Forum Synopsys - semtech - featimg

Accelerating multi-corner multi-mode sign-off using the Lynx Design System

Mixed-signal chip designer Semtech on using Lynx Design System to manage multi-corner multi-mode sign-off when you've got 306 scenarios to check.
Article  |  Tags: , , , ,   |  Organizations:
April 16, 2014
Pranav Ashar

Reset optimization pays big dividends before simulation

Reset is no longer simply an 'X' issue but also feeds into power optimization. Catching issues early greatly speeds verification.
Expert Insight  |  Tags: , ,   |  Organizations:
April 16, 2014
Real Intent hierarchical CDC

Hierarchy provides a smarter approach to SoC CDC verification

Performing clock-domain crossing (CDC) checks on a flat database is difficult on complex SoCs. Hierarchy improves speed but calls for a smarter approach.
Article  |  Tags: , ,   |  Organizations:
March 24, 2014
HAPS-DX

Prototyping solutions for validation of complex ASIC IP

An in-depth look at the role of FPGA-based prototyping and the validation use cases it offers when integrating complex blocks.
Article  |  Tags: , ,   |  Organizations: ,
March 17, 2014
Chris Tice is corporate vice president and general manager of hardware system verification at Cadence Design Systems

The rise of hardware-assisted verification

Verification of hardware and software has become a key bottleneck for chip design. Hardware-assisted verification is removing that bottleneck.
Expert Insight  |  Tags: ,   |  Organizations:
February 27, 2014
Warren Stapleton is a Senior Fellow in AMD’s verification methodology team.

Next wave of innovation in verification technology must come from integration

The next boost to verification productivity will come from the integration of multiple strategies and tools.
Expert Insight  |  Tags: , ,   |  Organizations:
February 26, 2014
Synopsys VCS Xprop feat

Catching X-propagation related issues at RTL

Catching x-propagation issues at RTL saves time and reduces uncertainty in gate-level verification
Article  |  Tags: , ,   |  Organizations:
February 26, 2014
Lisa Piper is senior manager of technical marketing at Real Intent.

Complexity drives smart reporting

Increasingly complex state machines are driving the need for smarter ways of reporting errors such as deadlocks and unreachable code in the source RTL.
Expert Insight  |  Tags: , , , , ,   |  Organizations:
February 6, 2014
Sudhakar Jilla is group marketing director for place & route at Mentor Graphics.

Concurrency tackles MCMM issues head-on

The number of scenarios needed for MCMM timing analysis has skyrocketed. IC implementation calls for a concurrent approach to deal with the issue.
Expert Insight  |  Tags: ,   |  Organizations:
February 4, 2014
Featured image - virtual prototyping big.Little case study

Debugging with virtual prototypes – Part Four

The fourth installment discusses the extra levels of debug capability available when using virtual prototypes through the example of an ARM big.LITTLE-based embedded system.
Article  |  Tags: , , , , , ,   |  Organizations: ,

PLATINUM SPONSORS

Mentor Graphics GLOBALFOUNDRIES Synopsys Samsung Semiconductor Cadence Design Systems
View All Sponsors