November 23, 2015
AMD VirtualBox hybrid emulation - featdiag

Enabling greater reliability, scalability and flexibility of GPU emulation at AMD using a hybrid virtual-machine based approach

How AMD coupled a virtual PC and transaction-based emulation to accelerate the verification of its latest GPU
November 2, 2015
Verification IP for greater productivity

How to cut verification time with VIP

This article shows practical ways to use verification IP for greater productivity with specific code examples from Mentor Graphics' Questa platform.
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October 29, 2015
Innovus chip layout

Cadence’s path to digital implementation on 10nm

The 10nm process will see changes to multiple patterning that demands changes in the implementation flow, along with an increased focus on the effects of variability.
October 28, 2015
Bruce McGaughy, CTO, ProPlus Design Solutions

FastSPICE simulators hit their expiration date

Although FastSPICE simulators are in almost every design flow, requirements are moving beyond the capabilities they can provide. Parallel processing provides a solution.
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October 21, 2015
HAPS cables 150

FPGA-based prototyping 3: Which board do I need?

Part three of our series looks at the choices you face as you decide whether to build or buy a board.
October 19, 2015
Nasib Naser is senior staff corporate applications engineer in the verification group for Synopsys.

Ten key tips for effective memory verification

Verification IP can help verify that memory-controller implementations meet standards; test an implementation against specific memories; and drive traffic for SoC verification and power analysis. Here's how to choose it.
October 8, 2015
Amol Herlekar, Synopsys

Preparing for low-power verification success: setting objectives and measuring outcomes

A look at what it takes to verify low-power SoC designs, including setting objectives and measuring outcomes in a UPF-driven verification strategy
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September 28, 2015
HAPS cables 150

FPGA-based prototyping 2: Understand the real cost

Part two of our series on FPGA-based prototyping looks at two critical factors to address before a project begins: budgeting and high-level implementation.
September 24, 2015
OneSpin HLS and formal verification

Linking high-level synthesis with formal verification

High-level synthesis provides a way to explore hardware architectures to come up with the most efficient implementation for a given situation. But it has taken time for verification techniques to catch up with the idea and ensure design and architecture match.
September 18, 2015
Featured image: PHY VIP Sep 15

How PHY verification kits overcome traditional VIP limitations

Established physical layer verification IP packages focus so much on protocols they miss problems that arise from the broader context. A PHY verification kit bridges the gap.
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