Verification

February 10, 2016
Geoffrey Ying, director of product marketing, AMS group, Synopsys

Speeding AMS verification by easing simulation debug and analysis

How to ease AMS verification using tools that improve simulation debug, ease IP integration, and speed design analysis and centering
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January 27, 2016
Dr Lauro Rizzatti, verification consultant

Hardware emulation answers Brooks’ Law

What can you add to a challenging project without pushing out deadlines and muddling communication?
January 26, 2016
Bus contention and floating bus issues featured image

Bus contention and floating busses: Catch them before simulation

Bus contention and floating busses are well defined issues and therefore excellent candidates for being addressed with early-stage formal verification.
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January 22, 2016
Verification IP, Mentor Graphics, Jan 16, Featured Image

Easing the use of APIs for verification IP stimuli

How to leverage a simpler, standardized approach to describing generic and reusable stimulus sequences for verification IP.
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January 20, 2016
End to end prototyping - featimg

Using end-to-end prototyping to reduce the impact of rising software content in SoCs

A look at using end-to-end prototyping to ease architecture development, hardware/software integration, and system validation in SoC designs
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January 19, 2016
Anders Nordstrom, senior corporate applications engineer, Verification Group, Synopsys

Reachable or reached, covered or coverable – is it just semantics?

How code coverage and reachability analysis differ between simulation and formal verification techniques, and ways to use that to advantage.
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January 18, 2016
How to debug and verify finite state machines early in the design flow

Finite state machines: How to debug and verify them early in the flow

Finite State Machines are such a familiar part of design, we can forget how often they generate errors. Learn how to address them quickly and most efficiently
January 5, 2016
Anders Nordstrom, senior corporate applications engineer, Verification Group, Synopsys

Thought you had verified your SoC? You probably only did half…

Using formal property verification to prove that SoCs can’t do the wrong thing, as well as that they will do the right thing.
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January 4, 2016
Interconnect variation in SoC

Timing analysis shifts to statistical

The 10nm process node calls for the use of SOCV techniques during timing signoff to avoid leaving too much performance on the table.
December 16, 2015
Fix X-pessimism with practical techniques by Lisa Piper

Fix X-pessimism in netlists with practical techniques

Traditional approaches do not catch all unknown state sources, lack capacity for big SoCs and mask bugs. Ascent XV addresses and overcomes these issues.

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