CDC violations are now so complex that it takes a combined block and full SoC level verification strategy to catch and fix all the bugs
Formal techniques can be applied to various parts of the verification challenge, including low-power and clock domain-crossing issues
Emulation and simulation acceleration technologies provide the means to more efficiently detect power issues before tapeout – and find the worst-case modes that need to be fixed.
Need to convince your FD of emulation’s growing ROI and the need to invest? Click here and ‘Forward’
Fab and IP vendor collaboration is making pattern matching-based libraries a vital component of DRC accuracy and efficiency. Learn how to take advantage.
This 'how to' guide shows how to combine the power of emerging and existing technologies for faster, more comprehensive test.
A look at a tool and a flow that makes it easier to put designs on to a HAPS physical prototyping system for verification, debug and software development purposes
Lint is no longer just about checking RTL code. It already incorporates functional verification within a three-stage analysis. Time to look again at a 'familiar' technology.
Innovation in physical verification is driven by incoming nodes but new tools and features can and should be fed back up the technology chain.
EDA vendors and internal CAD teams use Verific parsers for tool development. Here's how one company developed its strategy for this popular technology.
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