Verification

June 18, 2017

Portable stimulus

Accellera's Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.
June 13, 2017
Emulation save-and-restore debug featured image

Hardware emulation gets smarter with save-and-restore for debug

Techniques previously unavailable during ICE or testbench acceleration can now greatly speed emulation debug in those modes.
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June 7, 2017
Diag 4

Staging virtual prototype bring-up for faster software development

How staging virtual prototype bring-up can accelerate the development of embedded software in complex systems.
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May 22, 2017
Ashish Darbari is director of product management at OneSpin Solutions.

Introducing Doc Formal: the journey so far

Our new columnist introduces himself and traces the progress of formal verification over the last two decades. Join the discussion.
May 8, 2017
Dr Walden Rhines is Chairman and CEO of Mentor - A Siemens Business

The Wally Rhines interview – Part One: Mentor as a Siemens business

Our extended fireside chat with Mentor Chairman and CEO Wally Rhines begins by canvassing his thoughts now the Siemens deal is done.
April 26, 2017
Sanjana Bhattacharya

Eight tips for performing effective unreachability analysis

Unreachability analysis can help find design code that can never be executed, helping verification engineers refine their coverage goals.
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April 21, 2017
Visual: cars speeding along a road

Accelerating the development of powertrain ECUs with virtual hardware

How virtual hardware can speed up many aspects of automotive system development, including architectural analysis, software development and verification
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March 28, 2017
Anders Nordstrom, senior corporate applications engineer, Verification Group, Synopsys

Are you testing your test?

Using formal core coverage to understand the effectiveness of formal coverage verification strategies in SoC design.
March 15, 2017
DVCon China takes place at the Parkyard Hotel, Shanghai on April 19th.

DVCon China launches this April in Shanghai

DVCon China general chair Andy Liu discusses Accellera’s new addition to its design and verification conference series (简体中文).
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March 9, 2017
Anders Nordstrom, senior corporate applications engineer, Verification Group, Synopsys

The art of abstraction

Successful FPV of large designs requires that parts of the design are abstracted. Learning how and where to apply abstractions will result in more proven properties and more bugs found.

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