Verification

August 21, 2015
Visual: cars speeding along a road

Why emulation performance doesn’t matter (on its own)

Emulation performance is a key metric in verification. But it is far from being the only consideration. How long it takes to get a design onto a verification platform and aspects such as debug are as important. These factors will control how verification platforms are deployed during a project's life cycle.
August 19, 2015
Jai Durgam, Synopsys

Make vs buy in automotive IP

A look at some of the quality and safety requirements that must be met when developing and applying semiconductor IP to the automotive sector.
Expert Insight  |  Tags: , , , , , ,   |  Organizations:
August 7, 2015
Automotive crash test

Improving functional safety of automotive systems using virtual prototyping

The increasing complexity of automative software is challenging the ability of established software testing strategies to demonstrate its functional safety. Here's how virtual prototyping can help.
Article  |  Tags: , , , , , ,   |  Organizations:
August 4, 2015
Mick Posner is Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions.

Building better debug facilities for bigger FPGA-based prototypes

The introduction of bigger FPGAs enables more complex prototypes - but makes debugging more of a challenge. Here's one way to address the issue.
Expert Insight  |  Tags: ,   |  Organizations: ,
July 10, 2015
Jim Thomas is director of software testing at specialist test and verification company TVS.

What hardware verification can learn from software development

What hardware designers can learn from software verification techniques such as agile, behaviour-driven development, code coverage and zero known defect strategies
Expert Insight  |  Tags: , , ,   |  Organizations:
June 30, 2015
Mark Handover is an applications engineer with Mentor Graphics

Back to basics – doing formal the right way

Considering design style, assertions, engines and coverage can help ease the development of an effective formal verification test plan
Expert Insight  |  Tags: , , ,   |  Organizations:
June 22, 2015
Synopsys MIPI verification featimg

Verifying MIPI interfaces in SoCs

Verifying MIPI interfaces including CSI-2, CPHY, DPHY, MPY, Unipro and the UFS host controller on complex SoCs - should you make or buy the necessary VIP?
Article  |  Tags: , , , , , , , ,   |  Organizations: ,
May 31, 2015
realintent-metastable-thm

Technology trends demand netlist-level CDC verification

Complex processes and aggressive synthesis interventions are increasing the risks of metastability, creating a need for netlist-level CDC verification
May 29, 2015
Mentor Graphics/Wilson Research Group Functional Verification Study

Smaller designs face greater risk of respins

Research study suggests the maturity of your verification flow determines the likelihood of first-pass success far more than the complexity inherent in design size.
May 11, 2015
Fast to slow CDC - featimg

Verifying clock domain crossings when using fast-to-slow clocks

A look at three techniques to verify the validity of signals moving between clock domains

PLATINUM SPONSORS

Mentor Graphics GLOBALFOUNDRIES Synopsys Samsung Semiconductor Cadence Design Systems
View All Sponsors