Verification

December 8, 2014
Block and SOC CDC verification - feat img

Overcoming complex CDC violations with a concurrent block and SoC-level verification flow

CDC violations are now so complex that it takes a combined block and full SoC level verification strategy to catch and fix all the bugs
December 1, 2014
VC formal tools featimg

Using formal techniques to help tackle SoC verification challenges

Formal techniques can be applied to various parts of the verification challenge, including low-power and clock domain-crossing issues
November 23, 2014
Cadence Palladium cluster

Acceleration homes in on power issues

Emulation and simulation acceleration technologies provide the means to more efficiently detect power issues before tapeout – and find the worst-case modes that need to be fixed.
November 6, 2014
Dr Lauro Rizzatti is an independent verification consultant. You can contact him at lauro AT rizzatti DOT com

The budget case for emulation

Need to convince your FD of emulation’s growing ROI and the need to invest? Click here and ‘Forward’
November 5, 2014
Pattern matching DRC featured image

How to use pattern matching to improve automatic waiver management

Fab and IP vendor collaboration is making pattern matching-based libraries a vital component of DRC accuracy and efficiency. Learn how to take advantage.
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October 28, 2014
Featured image for hybrid testbench article

Harness virtual machines to create an efficient ‘live’ hybrid testbench

This 'how to' guide shows how to combine the power of emerging and existing technologies for faster, more comprehensive test.
October 15, 2014
ProtoCompiler featimg

Accelerating ‘time to prototype’ with ProtoCompiler

A look at a tool and a flow that makes it easier to put designs on to a HAPS physical prototyping system for verification, debug and software development purposes
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September 30, 2014
Pranav Ashar

The evolution of lint

Lint is no longer just about checking RTL code. It already incorporates functional verification within a three-stage analysis. Time to look again at a 'familiar' technology.
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September 10, 2014
John Ferguson is the director of marketing for Calibre DRC applications at Mentor Graphics. John has worked extensively in the area of physical design verification for the manufacture of leading edge integrated circuits.

If we’d only known then what we know now

Innovation in physical verification is driven by incoming nodes but new tools and features can and should be fed back up the technology chain.
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August 29, 2014
Verific Featured Image

Exploiting Verific tools and features at the right abstraction level

EDA vendors and internal CAD teams use Verific parsers for tool development. Here's how one company developed its strategy for this popular technology.
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