Verification

July 22, 2014
The evolution of software debug using hardware emulation

The evolution of software debug using hardware emulators

We look at how best to leverage both software debug tools and emulators, the limitations to traditional techniques, and the drive toward offline debug.
Article  |  Tags: ,   |  Organizations:
July 21, 2014
ADAS

When failure is not an option in automotive verification

The ISO 26262 safety standard lays out a number of best practices for the automotive industry and for suppliers. Formal verification provides a way of streamlining the verification of SoCs that need to conform to the standard.
Article  |  Tags: , , , ,   |  Organizations:
July 20, 2014
Rebecca Lipon is the senior product marketing manager for the functional verification product line at Synopsys. Prior to joining the marketing team, Rebecca was an applications engineer at Synopsys working on UVM/VMM adoption, VCS, VIP, static and formal verification deployments.

Rethinking SoC verification

The argument for an integrated approach to SoC verification
July 15, 2014

Parasitic extraction

Parasitic extraction reveals the impact of implementation on the theoretical performance of IC designs.
July 3, 2014
Pranav Ashar

It’s time to embrace objective-driven verification

How Wall Street's vastly resourced IT teams already point the way to cheaper, faster and more efficient verification by putting goals not tools first.
June 30, 2014
Future of thermal simulation

The future of thermal simulation for electronics products

Complexity and the increasing use of thermal analysis software by non-expert designers demands new approaches for chip and PCB implementations.
June 15, 2014
Chips on a wafer

Early tape-out: smart verification or expensive mistake?

Is it worth trying to iron out all the bugs in an SoC before taping out, or should design teams anticipating a re-spin go to silicon earlier and use the chips that come back as verification accelerators?
May 29, 2014

Lint

A static-analysis tool that checks for errors in HDL code, lint is becoming an increasingly important addition to simulation for RTL and SoC signoff.
May 28, 2014

Formal verification

As designs get larger and stress the ability of simulation to exercise an SoC, formal techniques have become essential parts of design and verification.
May 24, 2014
Dopant-level trojan standard cell developed by Georg Becker and coworkers

Hardware trojan attacks and countermeasures

IC designers are becoming increasingly worried about the possibility of third parties inserting malicious 'trojan' circuitry into their ICs.

PLATINUM SPONSORS

Mentor Graphics GLOBALFOUNDRIES Synopsys Samsung Semiconductor Cadence Design Systems
View All Sponsors