Verification

April 20, 2016
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Accelerating Android bring-up using VDKs in the LAVA framework

Accelerating software testing is vital to speeding up embedded system development, especially for Android and Linux systems running on ARM-based hardware. Virtual prototyping strategies, including the use of VDKs, can help.
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April 14, 2016
Victor Reyes, technical marketing manager, System Level Solutions group, Synopsys.

Scaling automated software testing with Virtualizer Development Kits

How to accelerate many aspects of software testing by using virtual prototypes to stand in for target hardware from early in the development cycle.
April 13, 2016
Shenoy Mathew is a senior corporate application engineer in the Verification Group, Synopsys.

The challenge of verifying the evolving Ethernet standard

A look at the challenge of Ethernet verification as data rates rise and the standard is applied in a wider variety of applications.
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April 6, 2016
Paul Graykowski, senior manager at Synopsys responsible for PCIe verification IP

Accelerating PCIe verification

A look at the challenges involved in PCIe verification as the standard evolves to 4.0 and beyond.
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March 9, 2016
Nissan Leaf electric car

Case study: Analyzing an electric vehicle powertrain using virtual FMEA

How the powertrain of an electric vehicle is modeled first in software, then elaborated using virtual hardware running target code, to enable virtual FMEA with rich data-gathering and analysis capabilities.
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March 3, 2016
Whats cooking at the Flash Diner - verification IP

What’s cooking at the Flash Diner?

Flash is the ice cream of memory technologies - everybody loves it. But you need to build the right verification environment to extract the greatest benefit.
March 1, 2016
Visual: cars speeding along a road

FMEA in automotive software development using virtual prototyping, physical modeling and simulation

How fault mode and effect analysis (FMEA) can be performed on a virtual prototype of an automotive system containing mechanical, electrical, analog and digital models, including the microcontroller running the same software as will be used in the car.
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March 1, 2016
Anders Nordstrom, senior corporate applications engineer, Verification Group, Synopsys

Exploiting the power of reset in formal verification

The reset state of a design can have a huge impact on the scope and correctness of verification, especially when formal techniques are applied.
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February 29, 2016
How to expose X-optimism issues in ASIC and FPGA Design by Lisa Piper

How to expose X-optimism issues in ASIC and FPGA design

Static analysis offers a powerful way of identifying potential X-optimism problems before simulation. The article defines the issue and describes an established solution.
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February 10, 2016
Geoffrey Ying, director of product marketing, AMS group, Synopsys

Speeding AMS verification by easing simulation debug and analysis

How to ease AMS verification using tools that improve simulation debug, ease IP integration, and speed design analysis and centering
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