Verification

May 15, 2019
Tom Anderson is a technical marketing consultant working with multiple EDA vendors, including AMIQ EDA. His previous roles have included vice president of marketing at Breker Verification Systems, vice president of applications engineering at 0-In Design Automation, vice president of engineering at IP pioneer Virtual Chips, group director of product management at Cadence, and director of technical marketing at Synopsys. He holds a Master of Science degree in Computer Science and Electrical Engineering from M.I.T. and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst.

Why hyperlinks are essential for HDL debugging

Text editors have major debug limitations that the use of hyperlinks in integrated development environments help you overcome.
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May 14, 2019

How emulation’s virtual mode boosts productivity: Part Two

Part two of this feature describes three use-cases that exploit the VirtuaLAB technology in HDMI, PCIe and Ethernet designs.
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May 1, 2019
Dr Lauro Rizzatti is a verification consultant and industry expert on hardware emulation. Gabriele Pulini is a product marketing manager in the Emulation Division of Mentor.

How emulation’s virtual mode boosts productivity: Part One

This two-part article describes advantages when using a hardware emulation platform in virtual mode compared with in-circuit-emulation.
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April 26, 2019
Portable Stimulus - Three Axes of reuse - Featured Image

Focus your use of Portable Stimulus on three key axes

Portable Stimulus allows reuse along horizontal, vertical and technique axes, but you need to be aware of the strengths and weaknesses of each to get the greatest benefits.
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March 25, 2019
Voltage-aware DRC featured image

Use evolving DRC to automate high-voltage and multi-power domain verification

Automated voltage-aware DRC addresses the reliability verification challenges in today’s high-voltage and multiple power domain applications.
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March 13, 2019
Liberty Variation Format - Featured Image

Validating on-chip variation: Is your library’s LVF data correct?

Machine learning techniques help ensure the validity of Liberty Variation Format information for OCV analysis at lower process nodes.
March 6, 2019
Ashish Darbari is CEO of formal verification consultancy Axiomise.

Doc Formal answers 11 key questions

The doctor was 'in' during last month's DVCon and here highlights some of the main issues in formal raised by delegates at the verification conference.
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March 1, 2019

Accelerating the implementation of application-specific processors

Application-specific processors can provide high performance for specialised tasks at low energy cost.
February 8, 2019
Featured image - Layout merging feature

Fast, accurate layout merging for SoC flows

How to achieve efficient merging of data from formats such as OASIS, GDS, and OpenAccess to ensure timely verification through DRC runs.
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February 6, 2019

Low-power debugging made easy

UPF provides a useful way to describe the power-management strategies that should be applied to a design, but using it introduces a number of challenges during low-power debugging.
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