signal integrity

October 18, 2017
Channel Operating Margin featured image

How Channel Operating Margin helps Gigabit Ethernet PCB analysis

The COM methodology is being extended and more widely adopted across high-speed designs thanks to deeper tool integration.
Article  |  Topics: PCB - Design Integrity, - PCB Topics  |  Tags: , , , , , , , ,   |  Organizations: ,
December 29, 2016
Danit Atar is a senior marketing programs specialist at Mentor Graphics

A reliability checklist for the Connected World

Reliability is growing to match security as a key challenge for PCB design. These tools and techniques will help you rise to it.
May 26, 2015
Simulated eye diagram of PAM3 signal for automotive Ethernet

Simulation predicts performance of automotive Ethernet

Ethernet is set to become one of the key communications standards for automotive. Early system-level simulation lets designers gauge performance before moving to hardware prototypes.
April 15, 2015
AIDT allows automated timing-alignment of PCB traces

Layout automation and simulation support DDR4 at lower system cost

The introduction of the DDR4 memory-bus standard will allow system designers to meet aggressive performance targets for their next-generation systems. But the changes required to support the higher datarates of DDR4 place stringent demands on the PCB designer.
Article  |  Topics: PCB - Design Integrity, Layout & Routing  |  Tags: , , ,   |  Organizations:
October 18, 2014
Soft-blocked floorplan

Placement optimizations push power and clock on Cortex-M7 project

Soft blocking to prevent cell spreading and other placement-optimization techniques helped improve power and clock speed on a Cortex-M7 test chip designed by ARM and Cadence.
June 10, 2014
High-speed I/O eye diagram - thumbnail

Zeroing in on the problems of fast board-level interconnect

A panel session at DAC 2014 focused on the problems of high-speed, board-level interconnect and the roles of codesign and power integrity in solving them.
March 6, 2014
Richard Goering, senior manager of technical communications, Cadence

Henny Youngman’s advice to PCB designers

In a standing-room-only talk at the recent DesignCon conference, Eric Bogatin explained why comedian Henny Youngman could help them with signal integrity on PCBs.
Expert Insight  |  Topics: PCB - Design Integrity  |  Tags: , ,   |  Organizations:
February 6, 2014
Sudhakar Jilla is group marketing director for place & route at Mentor Graphics.

Concurrency tackles MCMM issues head-on

The number of scenarios needed for MCMM timing analysis has skyrocketed. IC implementation calls for a concurrent approach to deal with the issue.
Expert Insight  |  Topics: EDA - IC Implementation, Verification  |  Tags: ,   |  Organizations:
May 8, 2013
Segement from PCB design rule schematic

Keeping high-speed designs clean with ERC

Electrical rule checks (ERC) are now available to deal with increasing PCB design complexity, speed project delivery and protect the intellectual property within them.
April 5, 2012

Overcoming increasing PCB complexity with automation

Advanced PCB and IC technologies have to be matched with advanced design and analysis tools if companies are going to produce board designs that are right first time, on time.

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