![AIDT allows automated timing-alignment of PCB traces](https://www.techdesignforums.com/practice/files/2015/04/cdns-aidt-allegro-sml-64x64.png)
Layout automation and simulation support DDR4 at lower system cost
The introduction of the DDR4 memory-bus standard will allow system designers to meet aggressive performance targets for their next-generation systems. But the changes required to support the higher datarates of DDR4 place stringent demands on the PCB designer.