PCIe 5.0

September 13, 2019

Introduction to the Compute Express Link (CXL) device types

A look at the device types defined by the Compute Express Link (CXL) standard.
Article  |  Topics: Embedded - Architecture & Design, IP - Selection  |  Tags: , , ,   |  Organizations:
September 12, 2019

Introduction to the Compute Express Link (CXL) protocols

A look at the key protocols that control the Compute Express Link (CXL) standard for connecting CPUs and accelerators in hetereogenous computing environments.
Article  |  Topics: Embedded - Architecture & Design, IP - Selection  |  Tags: , , , , , ,   |  Organizations:
September 11, 2019

Introducing the Compute Express Link (CXL) standard: the hardware

A guide to the emerging Compute Express Link (CXL) standard, which links CPUs and accelerators in heterogenous computing environments.
Article  |  Topics: Embedded - Architecture & Design, IP - Selection  |  Tags: , , ,   |  Organizations:
February 27, 2018
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Tackling the design challenges of PCIe 5.0

Moving up to PCIe 5.0 speeds demands rethinking everything from silicon design through choice of PCB material and connectors up to track layout and validation.

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