DAC 2015: Mentor Graphics at the Design Automation Conference
Review highlights from Mentor's activities at DAC and grab your last chance to register for in-depth technical sessions.
IP
COMPUTEX 2015: Wrap 1 – Is ‘The Internet of Things’ that helpful an idea?
Everybody knows the words. Everybody has a different definition. Did calling the next big thing 'The Internet of Things' actually create a hindrance not a help?
COMPUTEX 2015: Taiwan and mainland China face off in IoT platforms
It wasn't just ARM and TSMC that launched a 55nm IoT platform this week. Across the Taiwan Strait, Brite and SMIC have unveiled a similar offering. The competition could tell us a lot about the IoT market's future.
COMPUTEX 2015: Acer founder urges Taiwan to shift focus to software
Stan Shih says the Internet of Things is forcing Taiwan to reconsider its traditional concentration on electronics hardware.
COMPUTEX 2015: Intel sets out battle plan for Thunderbolt I/O
Thunderbolt speed to double to 40GBit/s, cheaper ownership for consumers, proprietary plug dumped in favor of USB-C as Intel looks to reinvigorate tech.
Heading to DAC? Why not head to the Love IP Party too
This year's Heart of Technology philanthropic event on Monday June 8 promises craft beers, music, a pool tournament and more, all supporting a great cause.
OneSpin uses app-store approach to open up formal verification
Formal-verification specialist OneSpin is setting up its own equivalent of an app store, building on top of a formal engine the company now licenses to other companies.
Imagination to extend virtualization across the SoC
Imagination Technologies plans to introduce support for virtualization across all its processor cores, including signal processors such as the Ensigma family, as part of a plan to improve SoC security.
Tortuga introduces security checks for SoC designs
Startup Tortuga Logic has developed a toolkit for checking the security aspects of SoC hardware designs.
Vehicle ethernet adds to IP virtual reference kits for board design
Automotive ethernet is the latest virtual reference design platform to be added to the family of models developed by Cadence to support its physical-layer IP cores.