DFT

How to save test time and test costs by doing more tests in parallel, increasing compression, pooling tester memory, managing branching - and more

Part three of our series looks at the choices you face as you decide whether to build or buy a board.

Part two of our series on FPGA-based prototyping looks at two critical factors to address before a project begins: budgeting and high-level implementation.

AMD's Radeon R9 family is the result of eight years developing 3D-IC and interposer technology. What lessons did the company learn?

Need to convince your FD of emulation’s growing ROI and the need to invest? Click here and ‘Forward’

This 'how to' guide shows how to combine the power of emerging and existing technologies for faster, more comprehensive test.

FInFET memories have different defects than those based on planar transistors. Here's how to test and repair them.

EDA vendors and internal CAD teams use Verific parsers for tool development. Here's how one company developed its strategy for this popular technology.

RTL sign-off strategies ease SoC design and IP integration by enabling early analysis and optimization of CDC, power, X propagation, timing, and resetability issues.

Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.