RTL

May 29, 2014

Lint

A static-analysis tool that checks for errors in HDL code, lint is becoming an increasingly important addition to simulation for RTL and SoC signoff.
Guide  |  Topics: EDA - Verification  |  Tags: , , , , , ,
April 5, 2012

Assertion-based verification

More than half of design companies claim to use ABV but many have yet to deploy full methodologies.

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