Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
Leading chip design analyst Gary Smith charts the course through the main questions dominating DAC 2011.
The article describes a methodology and appropriate code for developing a reset strategy that will work within a verification process. Specifically, the proposal has been drafted within the terms of the Open Verification Methodology.
Constrained random testbenches excel at quickly hitting the majority of coverage but their effectiveness trails off as coverage closure nears completion. This paper describes a testbench API that sits on top of OVM sequences allowing the existing constrained random infrastructure to be guided, enabling faster, more efficient coverage closure. Design and verification engineers can use [...]
When microprocessor core developer ARM started in a barn outside Cambridge, England, just over fifteen years ago, odds were against it making a global impact. The team of “12 engineers and me”, as then CEO and now chairman Sir Robin Saxby puts it, “had no patents, a working prototype and £1.75m of cash.” Without the […]