Automated formal technologies can be used to ease the debug and functional verification burden of SystemC/C++ code prior to high-level synthesis. This tutorial, first presented at DVCon Europe explores how these formal techniques can be deployed and provides real-world examples.
Learn how Calibre 3D enables circuit and layout verification multi-die assemblies so that heterogeneous die processes can co-exist without significant impact to the deck.
Pre- and post-processing EDA techniques help streamline design rule checks and delivery efficient waivers to speed design and debug.
PIM memory boosts efficiency by operating on data without moving it to the CPU but realizing this type of novel technology posed power integration and planning challenges.
Innovation is extending the technique's power across areas such as context-aware layout, accounting for multi-patterning and implementing fill.
Delivering physical implementations at new process nodes is getting ever harder. Learn how to stay on track by checking work is rule-compliant as you go.
SiP promises advances in transmission speeds, bandwidth, accuracy and low power but verification requires careful evolution of existing tools.
How to carry out a sensible analysis of cloud EDA's potential, so you get the right tools and computational resources to deliver increasingly complex designs.
Creating strong links between the electrical and mechanical design domains is a leading enabler of digitalization.
Learn how to bring together your NLDM and CCS models to reach timing closure faster with Solido Analytics.
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