ARM

May 15, 2015
Four-core Cortex-A72 layout example

Cortex-A72: microarchitecture tweaks focus on efficiency

ARM has revealed a number of details of the microarchitecture that underpins its flagship Cortex-A72 as the processor moves towards its production release.
May 6, 2015

Fixing late ECOs in ARM core subsystems at STMicroelectronics

Using equivalence checking to validate ECOs in ARM core subsystem development at STMicroelectronics
March 16, 2015
Brian Fuller is editor in chief at Cadence Design Systems.

Design reaches out from the edge

We are moving towards a "continuum of compute", ARM CEO Simon Segars said at CDNLive Silicon Valley, a trend that will reshape design.
October 28, 2014
Featured image for hybrid testbench article

Harness virtual machines to create an efficient ‘live’ hybrid testbench

This 'how to' guide shows how to combine the power of emerging and existing technologies for faster, more comprehensive test.
October 18, 2014
Soft-blocked floorplan

Placement optimizations push power and clock on Cortex-M7 project

Soft blocking to prevent cell spreading and other placement-optimization techniques helped improve power and clock speed on a Cortex-M7 test chip designed by ARM and Cadence.
October 6, 2014
Power grid signal track blocking

ARM, TSMC design explores 16nm finFET issues

ARM and TSMC used an extensive pre-planning process, including a static analysis of each module's overall logic structure, to put together a 2.3GHz processor design based around ARM's main 64bit Big.Little pairing for the foundry's 16nm finFET process.
Article  |  Topics: EDA - IC Implementation  |  Tags: , , , , ,   |  Organizations: ,
February 4, 2014
Featured image - virtual prototyping big.Little case study

Debugging with virtual prototypes – Part Four

The fourth installment discusses the extra levels of debug capability available when using virtual prototypes through the example of an ARM big.LITTLE-based embedded system.
September 10, 2013

Debugging with virtual prototypes – Part One

The first in a series of articles about using virtual prototyping techniques to achieve more effective debug.
Article  |  Topics: Embedded - Integration & Debug, EDA - Verification  |  Tags: ,   |  Organizations: , , ,
August 25, 2013
Tim Whitfield, director of engineering, ARM Taiwan

Proving the 20nm ecosystem with the ARM Mali GPU

What ARM learnt when it ran a Mali GPU-based test chip through a Synopsys tool flow onto a TSMC 20nm process
February 5, 2013

Using VIP for cache coherency hardware implementations

Cache coherency implemented in hardware increases the verification effort. VIP-based strategies are described with particular reference to ARM protocols.
Article  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations: ,

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