Using equivalence checking to validate ECOs in ARM core subsystem development at STMicroelectronics
We are moving towards a "continuum of compute", ARM CEO Simon Segars said at CDNLive Silicon Valley, a trend that will reshape design.
This 'how to' guide shows how to combine the power of emerging and existing technologies for faster, more comprehensive test.
Soft blocking to prevent cell spreading and other placement-optimization techniques helped improve power and clock speed on a Cortex-M7 test chip designed by ARM and Cadence.
ARM and TSMC used an extensive pre-planning process, including a static analysis of each module's overall logic structure, to put together a 2.3GHz processor design based around ARM's main 64bit Big.Little pairing for the foundry's 16nm finFET process.
The fourth installment discusses the extra levels of debug capability available when using virtual prototypes through the example of an ARM big.LITTLE-based embedded system.
The first in a series of articles about using virtual prototyping techniques to achieve more effective debug.
What ARM learnt when it ran a Mali GPU-based test chip through a Synopsys tool flow onto a TSMC 20nm process
Cache coherency implemented in hardware increases the verification effort. VIP-based strategies are described with particular reference to ARM protocols.
20nm test needs new approaches to cope with short delay defects, new memory failure mechanisms and the consequences of test compression strategies
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