UK consortium tapes out cryo-SRAM
A UK cryogenic-CMOS research project has taped out its first demonstrator chip for core memory IP expected to be able to operate at close to absolute zero.
SRAM
UK consortium starts work on cryogenic CMOS
A £6.5m grant will fund the development of memories and other IP to improve the control of qubits in quantum computers.
SureCore provides 30-day test for SRAM compiler
SureCore has started running 30-day trials of its low-power memory compiler.
SureCore SRAM tuning service aims for lower power
SureCore is introducing an IP customization service intended to deliver SRAM cores tuned to specific power and performance requirements for wearable, wireless, augmented reality, and IoT devices.
Pillar transistor points to smaller SRAMs at 5nm
Imec and Unisantis Electronics have developed a process flow based on a vertical transistor with a gate on all sides they claim will lead to denser memories on a 5nm node.
eSilicon to cut costs of ASIC development for IoT, other markets
Online portals enable ASIC designers to explore IP and delivery options, enabling lower-cost markets such as IoT
SureCore picks up grant for low-power, nanometer SRAM IP
Physical-IP startup SureCore has been awarded $380,000 to build a demo chip for a low-power SRAM design the company is aiming at finFET and FD-SOI processes.