Mentor zooms in on power peaks with emulator interface
Mentor Graphics has released a programming interface to its Veloce emulators intended to support faster and more accurate power estimation.
power intent
Sonics readies fine-grained power-gating architecture
Sonics is moving into power management with an approach intended to substantially automate much of the job of building finely grained power-gated SoCs.
Jasper, Duolog bring formal verification to IP specification and assembly, low-power design
Deal creates methodologies and tools to help deliver IP and SoC assemblies verified using formal methods. Low-power verification strategy also launched.
DAC 2012: Atrenta to automate production of power-intent constraints
Atrenta is updating existing tools and planning new ones to help designers get the most bang for their joule.