Cadence culls zeroes for faster neural throughput
Cadence has launched an AI processor using an designed to take advantage of the sparse structure of typical deep neural networks.
Cadence has launched an AI processor using an designed to take advantage of the sparse structure of typical deep neural networks.
The LightSuite Compiler produces designs based on Python descriptions and certifies them DRC-clean through hooks into the market-leading Calibre DFM suite.
GlobalFoundries has decided to put development of its 7nm process on the backburner and focus on its existing finFET and FD-SOI processes.
Collaboration on DTCO offers IBM a better way to evaluate combinations of transistor architectures, materials and other process technology innovations using design metrics, before real wafers become available for physical experimentation.
Tanner’s focus on AMS, MEMS and, now, the IoT-edge are making it even more ripe for integration with other Mentor tools.
Research institute Leti and low-volume wafer service CMP are cooperating on a project to let fabless chipmakers explore the use of non-volatile resistive RAMs in their designs.
How are Siemens’ internal investments in Mentor to fuel innovation and integration stacking up alongside the boost it has given for M&A?
Mentor has added three companies since its acquisition a little over a year ago – and there’s method to this buying spree.
Faster PHYs needed to shift vast amounts of data around giant data centres.
The rapid growth of interest in machine learning and artificial intelligence has prompted Synopsys to bring all its AI IP together in a microsite and brochure.