Formal engines learn from experience
Cadence and OneSpin are applying various forms of machine learning to their tools to automate formal verification.
Tech Design Forum Briefing
Briefing Authors
Paul Dempsey
Paul Dempsey has been a technology journalist for 20 years. His work has also appeared in EETimes, Red Herring and specialist journals published by the Financial Times.
Luke Collins
Luke Collins is a freelance technology journalist with 22 years’ experience. He is a former Editor-in-Chief of Electronics Times in the UK, and co-founded the IP9x series of conferences.
Chris Edwards
Chris Edwards has spent two decades covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology.
ES Design West outreach attracts launch participants
EDA and IP supporters of the new event see the goal of greater integration with the electronic systems supply chain as fundamental to their involvement.
The evolution of the digital twin
A digital twin is now more than just a virtual copy of a product. For Siemens, it is a multilayered concept powering a ‘boundary-free innovation platform’.
HOT 2019 moves alongside ESDesign West
Jim Hogan’s annual charity fundraiser, Heart of Technology, will this year be held on July 9 in San Francisco alongside SEMICON West.
May meeting to push for UVM analog extensions
Accellera is trying to standardize extensions to UVM for mixed-signal design.
Machine learning and chiplets headline VLSI Symposia
Large-scale MCMs and novel device architectures bookend the papers on machine learning at VLSI Symposia in an event that will also cover chiplet integration and other topics.
User2User Silicon Valley is two weeks away
Mentor’s technical conference will take place on May 2 at the Santa Clara Marriott and feature more than 45 user and vendor presentations.
ES Design West aims to showcase EDA to a widening world
ES Design West holds its first edition at San Francisco’s Moscone Center colocated with SEMICON West in July.
Boost your DFT efficiency for AI silicon design
Three hierarchical DFT strategies help cut time-to-market for large AI chips by exploiting regularity and addressing test at the RTL.
DesignWare gets automotive boost with GLOBALFOUNDRIES 22FDX SOI qualification
Synopsys and GLOBALFOUNDRIES are developing a portfolio of automotive IP for the chipmaker’s 22nm fully depleted silicon-on-insulator (22FDX) process.