Paul Dempsey has been a technology journalist for 20 years. His work has also appeared in EETimes, Red Herring and specialist journals published by the Financial Times.
Luke Collins is a freelance technology journalist with 22 years’ experience. He is a former Editor-in-Chief of Electronics Times in the UK, and co-founded the IP9x series of conferences.
Chris Edwards has spent two decades covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology.
You can now get a complete system-level flow, but bundling ‘free’ ESL with RTL tools slows the methodology shift, says the leading design analyst. Meanwhile, Cadence moves into the number two vendor slot, but the battle rages on.
The Mentor chief discusses ESL-based low power, emulation, 32nm to 20nm and using tools in the cloud.
Ambipolar FETs, which can be n or p-type dependent on a control gate, could offer a new way to design circuits at 20nm and below.
Reviewing some of the sector’s main trends with Susan Peterson, group director for VIP at the market leader.
How and why Huawei’s Hisilicon and DSP specialist CEVA tapped Cadence to implement ARM protocols.
Mentor Graphics has added to its HyperLynx suite a tool that uses design-rule check (DRC) techniques rather than simulation to look for potential signal-integrity problems.
Using a tile-based analog design methodology to produce power application controller ICs at Active-Semi
STMicroelectronics offers 28nm process to smaller scale users through CMP and Soitec
New features provide enhanced formal checking analysis, code coverage closure and extended clock domain crossing analysis.
16nm Pathfinder design kits next February and risk production from November 2013. Benchmarked to a 40% increase in speed, 50% reduction in power, and 60% reduction in area.