Verification

June 1, 2006

Addressing the design closure crisis

Why are more chips late to market and cost three times more to design at 90-nanometer (nm) than at 130nm? Today’s ASSPs and ASICs are huge, approaching one billion transistors, with clock speeds exceeding 1-GHz. Engineers struggle to manage the complexity of devices that achieve these levels of performance and size. A natural reaction to […]

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March 1, 2006

Have your cake and eat it: the future of simulation and verification

T he explosion in consumer electronics, especially in the wireless/handheld devices marketplace, has placed a tremendous technical and business burden on engineers in the design of these products. Design teams carry the responsibility of catering to often conflicting and always challenging product specifications. The product needs to be optimized on multiple demand vectors with little […]

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March 1, 2006

Integrated, comprehensive assertion-based coverage

Introduction The emergence of the SystemVerilog and PSL assertion languages promises to improve the effectiveness of existing verification flows. First, assertions give better local observability of the functionality they represent. Second, the assertions augment the textual specification to provide a more formal, executable representation of the functionality. Third, since the assertion languages have common semantics […]

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December 1, 2005

Analog verification IP and the next stage in the evolution of system-on-chip

Introduction Considerable effort is being exerted to improve the quality and success of system-on-chip (SoC) designs. Given the demand for more and more features, lower power requirements, and need for blazing speeds to handle increasing data for video and other hungry applications, it is no surprise that complex SoCs are becoming harder to verify. A […]

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June 1, 2005

SystemVerilog is changing everything

Considering how complexity has grown over the last 20 years, it is amazing how few dramatic shifts in the design and verification methodology have occurred. When they do happen — mylar to layout tools, gates to RTL, hand-crafted test vectors to testbench automation — they make our work as engineers easier and enable us to […]

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June 1, 2005

Formal verification poised for rapid growth

Design teams are becoming increasingly concerned at the growing disparity between the capacity of silicon in the latest processes and the design and verification capabilities of simulation tools. A number of trends are now converging to enable a step function increase in verification to complement and extend the debug and verification capabilities of HDL simulators. […]

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June 1, 2005

The ultimate wish-list

If you want to get a clear idea of just what is taxing engineers at any given time, you can do a lot worse than following the trends that emerge before each annual Design Automation Conference (DAC). “And this year, it is pretty clear that there are three things on everyone’s mind: power, system-level design […]

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