Verification

April 25, 2012
Mentor's Veloce emulator

Emulation delivers energy efficiencies and economies of scale

Can emulation save energy and space, as well as time, during the verification process? Some argue so.
April 25, 2012
Richard Pugh

No more spaghetti

Richard Pugh reflects on efforts to cut through the tangle of cables and make emulation easier.
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April 24, 2012

What can FPGA-based prototyping do for you?

This extract from the Synopsys and Xilinx-authored "FPGA-Based Prototyping Methodology Manual" outlines a number of valuable strategies supported by brief project case studies.
April 10, 2012

Using assertions in ‘elemental analysis’ for airborne hardware development – Part Two

The article continues the discussion of the verification requirements within the RTCA DO-254 design assurance guidelines. Part Two focuses on assertion-based verification. It proposes a method for using ABV to meet 'elemental analysis' requirements and underpin a systematic approach to robustness testing.
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April 5, 2012

Assertion-based verification

More than half of design companies claim to use ABV but many have yet to deploy full methodologies.
April 5, 2012

FPGA prototyping

Building a prototype SoC in one or a set of FPGAs can aid field trials, software development and hardware/software integration. But it's not easy, so the decision to go ahead needs careful consideration.
March 28, 2012

Verification IP

Verification IP is becoming an increasingly important component for system design due to the rapid proliferation of new protocols and interfaces, chiefly driven by mobile comms.
March 20, 2012

Blindsided by a glitch

Logic glitches in asynchronous clock domain crossing paths can arise even when synthesis tools declare a design’s RTL and gate-level netlists equivalent. This article describes Real Intent’s approach to capturing them.
March 19, 2012

RTL debug: integrating automation and vizualization

Root-cause analysis of detected errors is a key design step. Debugging can take more than half of the verification effort. Vennsa’s OnPoint automated debug technology has been integrated with Springsoft’s Verdi visualization platform to reduce cost and uncertainty.
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March 7, 2012

Three essential steps to SoC design and verification

An evolved ESL-to-RTL methodology flow addresses the ‘discipline gaps’ between software and hardware engineering by using three system level-based software-hardware verification steps. The strategy is already available in TSMC’s Reference Flow 12.

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