RAID vendor Dot Hill adopts OVM flow for reliability
How the company migrated to an OVM-based methodology to design and verify a 30 million-gate ASIC design, on the path to UVM.
Verification
Formal techniques tackle the SoC verification challenge
Formal verification techniques are becoming more widely used as the size and complexity of SoCs and increases.
The challenge of clock domain crossings – and some solutions
Clock domain crossing bugs undermine the productivity gains of moving to block-based design, but can be tackled through hierarchical formal analysis.
IEEE 1801-2013 (UPF 2.1)
IEEE 1801-2013 updates and refines the Unified Power Format for low-power VLSI design, reflecting changes in power modeling and verification.
Facing the verification management challenge
The growing verification challenge, and how to address it by coordinating multiple debug strategies.
Building an RTL sign-off flow
RTL sign-off strategies ease SoC design and IP integration by enabling early analysis and optimization of CDC, power, X propagation, timing, and resetability issues.
Better analysis helps improve design quality
Better upfront analysis can help avoid propagating errors from RTL into the netlist, and reveal a number of ways to improve the quality of your final design.
Physical verification of finFET and FD-SOI devices
A look at some of the design and physical verification challenges of working with finFET and FD-SOI devices, including their impact on layout, DRC and LVS.
IP-to-SoC prototyping demands consistency
Many problems arise during the IP-to-SoC phase of FPGA-based prototyping due to the mix-and-match nature of the prototypes not the actual designs.
Debugging the debug challenge
Debug of logic and testbench debug makes up 35% of chip design, and is growing as power-management and hardware/software issues become part of the task.