Verification

November 16, 2012
Synopsys Virtualizer screen shot

The Shift Left: how virtual prototyping reduces risk

The business case behind how virtual prototyping speeds development, improves hardware and software quality, and improves ROI.
Article  |  Tags: , ,   |  Organizations:
October 30, 2012
Mixed-Signal Methodology Guide

Verifying low-power intent in mixed-signal design

An exclusive extract from Cadence Design Systems' Mixed-Signal Methodology Guide provides an excellent overview of its discrete topic and a flavor of the book as a whole.
Article  |  Tags: , , ,   |  Organizations: ,
October 26, 2012

Emulation delivers system-level power verification

Overcome the time and visibility limitations of simulation and of gate-level and RTL-based strategies to achieve full-chip analysis.
Article  |  Tags: , , , ,   |  Organizations:
October 3, 2012

System virtual prototyping

The technique enables early software development and hardware/software co-design strategies before a project is more rigidly defined in RTL.
September 18, 2012
Bill Neifert

Virtual prototyping moves further into the mainstream

Carbon Design Systems' CTO Bill Neifert argues that his company's deal with Samsung sends a clear signal, whether or not you're one of his customers.
Expert Insight  |  Tags:
September 14, 2012

Moving to advanced reliability verification

Shrinking process nodes, rising power efficiency goals and burgeoning device functionality are stretching existing DFR techniques to their limits. This scalable methodology looks to address the shortfall.
Article  |  Tags: ,   |  Organizations: ,
August 23, 2012
Pranav Ashar

Verification challenges require surgical precision

The verification challenge is best addressed by a combination of highly targeted tools, according to Pranav Ashar, CTO of Real Intent.
July 26, 2012

Synthesizing assertions into hardware for faster silicon debug

Assertions are already used in pre-silicon verification and can help halve debug time. So why not synthesize assertions into real logic gates in the final silicon, to catch those unexpected bugs that make validation so much harder? Here’s how.
Article  |  Tags: , ,   |  Organizations:
May 28, 2012

Emulation

The value of the emulation market has almost doubled in the last four years as the technique becomes increasingly valuable to hardware/software co-verification.
May 21, 2012

Where there’s a will… there’s a way to better VHDL verification

An overview of the Open Source VHDL Verification Methodology and two of the libraries it uses.

PLATINUM SPONSORS

Synopsys Cadence Design Systems Siemens EDA
View All Sponsors