Verification

The business case behind how virtual prototyping speeds development, improves hardware and software quality, and improves ROI.

An exclusive extract from Cadence Design Systems' Mixed-Signal Methodology Guide provides an excellent overview of its discrete topic and a flavor of the book as a whole.

Overcome the time and visibility limitations of simulation and of gate-level and RTL-based strategies to achieve full-chip analysis.

The technique enables early software development and hardware/software co-design strategies before a project is more rigidly defined in RTL.

Carbon Design Systems' CTO Bill Neifert argues that his company's deal with Samsung sends a clear signal, whether or not you're one of his customers.

Shrinking process nodes, rising power efficiency goals and burgeoning device functionality are stretching existing DFR techniques to their limits. This scalable methodology looks to address the shortfall.

The verification challenge is best addressed by a combination of highly targeted tools, according to Pranav Ashar, CTO of Real Intent.

Assertions are already used in pre-silicon verification and can help halve debug time. So why not synthesize assertions into real logic gates in the final silicon, to catch those unexpected bugs that make validation so much harder? Here’s how.

The value of the emulation market has almost doubled in the last four years as the technique becomes increasingly valuable to hardware/software co-verification.

An overview of the Open Source VHDL Verification Methodology and two of the libraries it uses.