Xilinx

August 5, 2015
Power switch

‘Even the software guys are starting to talk in milliwatts’

System-level power is the next frontier for a power-intent standard – or rather a collection of them – being developed by a partnership between Accellera, Si2 and the IEEE.
August 4, 2015
Mick Posner is Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions.

Building better debug facilities for bigger FPGA-based prototypes

The introduction of bigger FPGAs enables more complex prototypes - but makes debugging more of a challenge. Here's one way to address the issue.
Expert Insight  |  Topics: EDA - Verification  |  Tags: ,   |  Organizations: ,
March 24, 2014
HAPS-DX

Prototyping solutions for validation of complex ASIC IP

An in-depth look at the role of FPGA-based prototyping and the validation use cases it offers when integrating complex blocks.
Article  |  Topics: IP - Assembly & Integration, EDA - Verification  |  Tags: , ,   |  Organizations: ,
August 12, 2013
Steve Smith of Synopsys

Help Wanted? Help Given! 3D-IC design is ready for take-off

3D-IC design is ready for take-off, following several years of intense collaboration to develop the necessary tools, methodologies and flows
Expert Insight  |  Topics: EDA - IC Implementation  |  Tags: , , ,   |  Organizations: , ,
December 12, 2012
Xilinx 3D-IC interposer featured image

Enabling 3D-IC design

Meeting the challenges of moving beyond planar integration to side by side, and eventually truly stacked, dice, for designers, tool vendors and the supply chain.
Article  |  Topics: EDA - IC Implementation  |  Tags: , , ,   |  Organizations: ,
November 16, 2012
Marco Casale-Rossi

3DIC – the advantages and the challenges of vertical integration

The advantages and challenges of 3D IC integration, as we add vertical functional integration options to the traditional planar integration brought by the progress of Moore's Law.
Expert Insight  |  Topics: EDA - IC Implementation  |  Tags: , , ,   |  Organizations: , , ,
October 25, 2012

Vivado HLS/AutoESL: Agilent packet engine case study

How Xilinx' Vivado HLS enabled the creation of an in-fabric, processor-free UDP network packet engine
October 23, 2012
tdf-xilinx1-oct12-featim

Vivado, inside the new Xilinx design suite

The FPGA vendor's new flagship is now on public release. It adds an array of features, including support for system-level to HDL synthesis.
July 5, 2012
tdf-jul12-flexras-feat

Improving ASIC prototyping on multiple FPGAs through better partitioning

Using a new design-partitioning tool and stacked-silicon interconnect FPGA to develop an ASIC prototyping platform that can be reprogrammed several times a day.
Article  |  Topics: EDA - DFM  |  Tags: , , ,   |  Organizations: ,

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors