Proving the 20nm ecosystem with the ARM Mali GPU
What ARM learnt when it ran a Mali GPU-based test chip through a Synopsys tool flow onto a TSMC 20nm process
IP Topics
Formal techniques tackle the SoC verification challenge
Formal verification techniques are becoming more widely used as the size and complexity of SoCs and increases.
Eliminating iterations in gigahertz ASIC handoff
How Cisco eliminated iterations in the ASIC handoff of a gigahertz networking chip by using physically aware synthesis
The challenge of clock domain crossings – and some solutions
Clock domain crossing bugs undermine the productivity gains of moving to block-based design, but can be tackled through hierarchical formal analysis.
Enabling greater productivity and schedule predictability in IC design
How to speed project start-up, boost designer productivity and increase schedule predictability using design management tools.
Facing the verification management challenge
The growing verification challenge, and how to address it by coordinating multiple debug strategies.
Building an RTL sign-off flow
RTL sign-off strategies ease SoC design and IP integration by enabling early analysis and optimization of CDC, power, X propagation, timing, and resetability issues.
IP-to-SoC prototyping demands consistency
Many problems arise during the IP-to-SoC phase of FPGA-based prototyping due to the mix-and-match nature of the prototypes not the actual designs.
Debugging the debug challenge
Debug of logic and testbench debug makes up 35% of chip design, and is growing as power-management and hardware/software issues become part of the task.
Improving SoC productivity through automatic design rule waiver processing for legacy IP
You can waive some physical verification errors related to legacy IP found in foundry DRC checks. Knowing which has involved lengthy manual analysis. TSMC is enhancing the process with automation.
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