IP Topics

February 10, 2016
Geoffrey Ying, director of product marketing, AMS group, Synopsys

Speeding AMS verification by easing simulation debug and analysis

How to ease AMS verification using tools that improve simulation debug, ease IP integration, and speed design analysis and centering
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January 22, 2016
Verification IP, Mentor Graphics, Jan 16, Featured Image

Easing the use of APIs for verification IP stimuli

How to leverage a simpler, standardized approach to describing generic and reusable stimulus sequences for verification IP.
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January 12, 2016
Angela Raucher is product line manager for Synopsys’ ARC EM processors.

Processor configuration for low-power IoT applications

Many IoT applications have a very strict energy budget. SoC designers targeting the IoT have to trade off providing the features that the market demands with the power budget the applications demand. What are their options?
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January 11, 2016

FPGA design for functional safety

Using triple modular redundancy, error detection and correction, and 'safe' FSMs to ensure greater functional safety in FPGA-based designs
December 17, 2015
USB Type C connector

Integrated IP supports cost-efficient USB Type-C

The arrival of USB Type C provides an opportunity for SoC design teams with opportunities to provide customers with significant cost savings. Integrated IP will help the process.
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November 24, 2015
Angela Raucher is product line manager for Synopsys’ ARC EM processors.

Taking an end-to-end approach to IoT security

Achieving IoT security means addressing every link in the chain, from the quality of your application code to embedding a root of trust in the hardware.
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October 19, 2015
Nasib Naser is senior staff corporate applications engineer in the verification group for Synopsys.

Ten key tips for effective memory verification

Verification IP can help verify that memory-controller implementations meet standards; test an implementation against specific memories; and drive traffic for SoC verification and power analysis. Here's how to choose it.
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October 8, 2015
Amol Herlekar, Synopsys

Preparing for low-power verification success: setting objectives and measuring outcomes

A look at what it takes to verify low-power SoC designs, including setting objectives and measuring outcomes in a UPF-driven verification strategy
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September 18, 2015
Featured image: PHY VIP Sep 15

How PHY verification kits overcome traditional VIP limitations

Established physical layer verification IP packages focus so much on protocols they miss problems that arise from the broader context. A PHY verification kit bridges the gap.
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August 26, 2015
Gervais Fong is a senior product manager for mixed-signal PHY IP at Synopsys.

USB Type-C: easier for users, harder for designers

Implementing the reversible connector of USB Type-C demands a rethink of the PHY architecture to achieve the most cost-effective IP solution
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