How to leverage a simpler, standardized approach to describing generic and reusable stimulus sequences for verification IP.
Many IoT applications have a very strict energy budget. SoC designers targeting the IoT have to trade off providing the features that the market demands with the power budget the applications demand. What are their options?
Using triple modular redundancy, error detection and correction, and 'safe' FSMs to ensure greater functional safety in FPGA-based designs
The arrival of USB Type C provides an opportunity for SoC design teams with opportunities to provide customers with significant cost savings. Integrated IP will help the process.
Achieving IoT security means addressing every link in the chain, from the quality of your application code to embedding a root of trust in the hardware.
Verification IP can help verify that memory-controller implementations meet standards; test an implementation against specific memories; and drive traffic for SoC verification and power analysis. Here's how to choose it.
A look at what it takes to verify low-power SoC designs, including setting objectives and measuring outcomes in a UPF-driven verification strategy
Established physical layer verification IP packages focus so much on protocols they miss problems that arise from the broader context. A PHY verification kit bridges the gap.
Implementing the reversible connector of USB Type-C demands a rethink of the PHY architecture to achieve the most cost-effective IP solution
The wearables market is booming. Successful development depends on assembling the right software and hardware tools. Here's a primer on what to look for.
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