IP Topics

January 26, 2023
3D IC workflow democratization

Give the people what they want: toward making 3D IC mainstream

Learn more about the five interconnected workflows that are democratizing next generation design in the emerging chiplet age.
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October 19, 2022
Stephen Chavez is a senior printed circuit engineer and a Senior Product Marketing Manager at Siemens EDA. Stephen is an IPC Certified Master Instructor Trainer (MIT) for PCB design, an IPC Certified Advanced PCB Designer (CID+), and a Certified Printed Circuit Designer (CPCD). He is chairman of the Printed Circuit Engineering Association (PCEA)

A three-phase strategy to master the supply chain tsunami

Knowledge, intelligence and optimization are key to managing the logistical disruption seen since the Covid-19 outbreak.
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January 12, 2022
Formal verification for SystemC thumbnail

Formal verification for SystemC/C++ designs

Automated formal technologies can be used to ease the debug and functional verification burden of SystemC/C++ code prior to high-level synthesis. This tutorial, first presented at DVCon Europe explores how these formal techniques can be deployed and provides real-world examples.
October 26, 2020
Featured image - cel-name conflict resolution

Resolving IP cell-name conflicts peacefully

One roadblock to the integration of IP from multiple vendors into an SoC is the likelihood of finding duplicate cell names in the merged design. Carefully considered renaming strategies can fix the problem without causing design database bloat.
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May 29, 2020
runtime monitoring featim

How to use runtime monitoring for automotive functional safety

The promise of autonomous vehicles is driving profound changes in the design and testing of automotive ICs.
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September 18, 2019

Implementing high performance, low power Bluetooth Low Energy interfaces in SoCs

A look at the complexiites of implementing a Bluetooth Low Eenergy interface in an SoC.
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September 13, 2019

Introduction to the Compute Express Link (CXL) device types

A look at the device types defined by the Compute Express Link (CXL) standard.
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September 12, 2019

Introduction to the Compute Express Link (CXL) protocols

A look at the key protocols that control the Compute Express Link (CXL) standard for connecting CPUs and accelerators in hetereogenous computing environments.
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September 11, 2019

Introducing the Compute Express Link (CXL) standard: the hardware

A guide to the emerging Compute Express Link (CXL) standard, which links CPUs and accelerators in heterogenous computing environments.
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September 3, 2019

Ensuring system-level security of complex SoCs

Using a hardware root of trust and a secure development lifecycle process to form the basis of a better approach to developing and implementing more secure complex SoCs.

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