Extract benefit from automated refactoring of VHDL code
VHDL has come a long way in terms of complexity. An integrated development environment helps you deliver better and more compliant code quickly.
Verification
P&R filler cell insertion slowing you down? Replace it
A physical verification-ready flow can speed project delivery by making your use of filler cells more efficient.
Everything you ever wanted to know about RISC-V architectural formal verification
But you were NOT afraid to ask.... It's time for some answers.
Creating a new paradigm for circuit verification
How Calibre is evolving to address the challenges of LVS verification in early-stage design.
EDA innovation is the foundation of progress
For physical verification and beyond, each process node requires new thinking, new tools and greater performance.
How IDEs enable the ‘shift left’ for VHDL
Learn how an IDE offers on-the-fly, auto-correct and informed analysis of VHDL code to speed project quality and delivery.
How to achieve fast, automated, sign-off verification of DFM hotspot fixes in P&R
A collaboration between GlobalFoundries and Mentor has resulted in an innovative in-design fixing strategy across markets such as IoT, mobile, RF, graphics and networking.
UVM coding guidelines offer clarity in a complex world
These 13 suggestions toward best practice address some of the most persistent challenges with the Universal Verification Methodology.
VHDL users also deserve efficient design and verification
More commonly associated with SystemVerilog, IDEs can also greatly help users of the popular HDL for FPGA, mil/aero and other designs.
Covid-19 rings changes for virtual working
Virtualization is becoming ever more common during the Covid-19 outbreak, even for complex technologies like emulation, and showing its strengths.
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