Verification

A look at some of the key techniques needed to ensue good code coverage during the verification of low-power SoC designs.

A look at ways to improve LVS debug productivity on complex SoCs through more narrowly targeted debug strategies.

The vision of portable stimulus is to find a way to write tests that can be portable ‘vertically’ from IP block to subsystem to system, and ‘horizontally’ from simulation to emulation to silicon. However, applying portable stimulus to real chip designs is not trivial.

Power intent files have increased efficiency and the use of an IDE can prevent them becoming outdated as a design evolves.

Autonomous vehicle functional verification needs to prove the predictable behavior, safety and security of complex SoCs and their associated software, sensors and actuators, demanding greater use of hardware emulation.

Accellera's Portable Test and Stimulus standard provides powerful features for verification that is not meant to replace UVM but augment existing verification flows. Here is how portable stimulus and UVM interact.

The Portable Stimulus Standard helps overcome many of the verification challenges inherent in the strict requirements of ISO 26262.

Refactoring saves time and resuources by converting code to a common format and eliminates redundancies to make it more readable and maintainable.

Doc Formal rounds up some of the the key observations about verfication made during July’s Synopsys VC Formal SIG event in India.

An IDE designed to catch typographical errors, missing declarations and inconsistent references in your code can hugely reduce your time in debug.