Verification

Refactoring saves time and resuources by converting code to a common format and eliminates redundancies to make it more readable and maintainable.

Doc Formal rounds up some of the the key observations about verfication made during July’s Synopsys VC Formal SIG event in India.

An IDE designed to catch typographical errors, missing declarations and inconsistent references in your code can hugely reduce your time in debug.

Doc Formal describes a strategy developed by his company Axiomise to apply formal verification proofs to open-source processor for safety, security and reliability.

How to remove or extract portions of a layout for easier, more focused and faster project delivery.

Text editors have major debug limitations that the use of hyperlinks in integrated development environments help you overcome.

Part two of this feature describes three use-cases that exploit the VirtuaLAB technology in HDMI, PCIe and Ethernet designs.

This two-part article describes advantages when using a hardware emulation platform in virtual mode compared with in-circuit-emulation.

Portable Stimulus allows reuse along horizontal, vertical and technique axes, but you need to be aware of the strengths and weaknesses of each to get the greatest benefits.

Automated voltage-aware DRC addresses the reliability verification challenges in today’s high-voltage and multiple power domain applications.