Verification

Symmetry verification for analog and custom IC needs to evolve beyond current time-consuming and hard-to-use techniques.

NVMe over Fabrics (NVMe-oF) extends the memory standard for burgeoning data traffic and the demands of AI and machine learning.

CDC-related metastability is hard to catch by hand and processes are error prone. Tools offer a more comprehensive approach.

Coordinate-based checking provides a streamlined way to verify designs around ESD before full-chip runs without the need for custom checks.

What are the options and how do you balance overarching CAD requirements and personal preferences?

Automating executable specifications as they evolve can deliver major efficiencies.

The Covid-driven MCU shortage for ECUs and elsewhere in vehicle design can bring entire production lines to a halt if not properly managed.

Because of the high analog content in memory designs, designers must understand how various effects impact reliability and performance.

Generating accurate ASIL metrics early in the functional safety lifecycle, reduces time-to-certification for ISO26262.

More optimistic about the semiconductor industries prospects than for some time, Siemens Joe Sawicki identified key EDA challenges at DAC.