Verification

March 13, 2019
Liberty Variation Format - Featured Image

Validating on-chip variation: Is your library’s LVF data correct?

Machine learning techniques help ensure the validity of Liberty Variation Format information for OCV analysis at lower process nodes.
March 6, 2019
Ashish Darbari is CEO of formal verification consultancy Axiomise.

Doc Formal answers 11 key questions

The doctor was 'in' during last month's DVCon and here highlights some of the main issues in formal raised by delegates at the verification conference.
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March 1, 2019

Accelerating the implementation of application-specific processors

Application-specific processors can provide high performance for specialised tasks at low energy cost.
February 8, 2019
Featured image - Layout merging feature

Fast, accurate layout merging for SoC flows

How to achieve efficient merging of data from formats such as OASIS, GDS, and OpenAccess to ensure timely verification through DRC runs.
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February 6, 2019

Low-power debugging made easy

UPF provides a useful way to describe the power-management strategies that should be applied to a design, but using it introduces a number of challenges during low-power debugging.
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January 16, 2019
Virtual sequences with portable stimulus - featured image.

Create more flexible virtual sequences with Portable Stimulus

Virtual sequences are considered challenging to write and re-use. Learn how to overcome those issues with the new Portable Stimulus Standard in this DMA-based case study.
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January 7, 2019
Ashish Darbari is CEO of formal verification consultancy Axiomise.

Doc Formal: Introducing the ADEPT FV flow

Escape formal's narrower definitions with a flow that shows you how to Avoid, Detect, Erase, Prove Absence and Tape Out while avoiding bugs.
December 11, 2018

Win on the fault campaign trail with formal

How formal verification for the ISO26262 automotive functional safety delivers the full activation, propagation, and observation in the form of proven and exhaustive results.
December 3, 2018
Rahul Chirania is a staff applications engineer with the static verification team at Synopsys.

Verifying clock domain crossings in UPF-based low-power SoCs

The verification challenges of using low-power design techniques to enable advanced power-management strategies in complex SoCs.
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November 20, 2018
HDAP_FeaturedImage

Adding system-level, post-layout electrical analysis to HDAP design and verification

Adoption of high-density advanced packaging (HDAP) needs tools and supports to build designers' confidence in the emerging technology.
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