Verification

CDC-related metastability is hard to catch by hand and processes are error prone. Tools offer a more comprehensive approach.

Coordinate-based checking provides a streamlined way to verify designs around ESD before full-chip runs without the need for custom checks.

What are the options and how do you balance overarching CAD requirements and personal preferences?

Automating executable specifications as they evolve can deliver major efficiencies.

The Covid-driven MCU shortage for ECUs and elsewhere in vehicle design can bring entire production lines to a halt if not properly managed.

Because of the high analog content in memory designs, designers must understand how various effects impact reliability and performance.

Generating accurate ASIL metrics early in the functional safety lifecycle, reduces time-to-certification for ISO26262.

More optimistic about the semiconductor industries prospects than for some time, Siemens Joe Sawicki identified key EDA challenges at DAC.

Automated formal technologies can be used to ease the debug and functional verification burden of SystemC/C++ code prior to high-level synthesis. This tutorial, first presented at DVCon Europe explores how these formal techniques can be deployed and provides real-world examples.

Learn how Calibre 3D enables circuit and layout verification multi-die assemblies so that heterogeneous die processes can co-exist without significant impact to the deck.