Verification

May 19, 2022
DO-254 CDC FeatIM

Fly the friendly skies with automated CDC verification for DO-254

CDC-related metastability is hard to catch by hand and processes are error prone. Tools offer a more comprehensive approach.
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May 10, 2022
Coordinate-based checks feature

A quick and easy way to calculate P2P resistance and current density

Coordinate-based checking provides a streamlined way to verify designs around ESD before full-chip runs without the need for custom checks.
April 28, 2022
James Paris is a senior product engineer with the Design to Silicon division of Siemens Digital Industries Software, supporting Calibre design interfaces. Prior to joining Siemens, he held roles in analog/mixed-signal physical design implementation and flow development for various IC design companies. James holds a BS in Computer-Aided Design Engineering and an MBA in Marketing.

Layout customization improves productivity in design and verification flows

What are the options and how do you balance overarching CAD requirements and personal preferences?
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March 21, 2022
Tom Anderson is a technical marketing consultant working with multiple EDA vendors, including AMIQ EDA. His previous roles have included vice president of marketing at Breker Verification Systems, vice president of applications engineering at 0-In Design Automation, vice president of engineering at IP pioneer Virtual Chips, group director of product management at Cadence, and director of technical marketing at Synopsys. He holds a Master of Science degree in Computer Science and Electrical Engineering from M.I.T. and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst.

Executable specifications boost SoC and IP efficiency

Automating executable specifications as they evolve can deliver major efficiencies.
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March 8, 2022
Brendan Morris is a senior technical marketing manager for the Integrated Electrical Systems group, Siemens Digital Industries Software. He spent his early career working in Automotive Tier 1 suppliers, working on a diverse range of technologies and vehicle types, including software development in powertrain electronics. He spent the next 10 years working for several vehicle OEM's at all stages of vehicle development programs. Brendan holds an M.Eng degree in Automotive Engineering from Loughborough University.

Use digitalization to mitigate the automotive MCU shortage

The Covid-driven MCU shortage for ECUs and elsewhere in vehicle design can bring entire production lines to a halt if not properly managed.
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March 3, 2022

Why comprehensive memory layout verification needs automated reliability checks

Because of the high analog content in memory designs, designers must understand how various effects impact reliability and performance.
January 27, 2022

Assure diagnostic coverage from RTL to gate level during analysis for functional safety

Generating accurate ASIL metrics early in the functional safety lifecycle, reduces time-to-certification for ISO26262.
January 13, 2022

Siemens’ Sawicki puts priority on scaling in processes, productivity and systems

More optimistic about the semiconductor industries prospects than for some time, Siemens Joe Sawicki identified key EDA challenges at DAC.
January 12, 2022
Formal verification for SystemC thumbnail

Formal verification for SystemC/C++ designs

Automated formal technologies can be used to ease the debug and functional verification burden of SystemC/C++ code prior to high-level synthesis. This tutorial, first presented at DVCon Europe explores how these formal techniques can be deployed and provides real-world examples.
December 15, 2021

Physical verification of package assemblies no longer hinders package adoption

Learn how Calibre 3D enables circuit and layout verification multi-die assemblies so that heterogeneous die processes can co-exist without significant impact to the deck.
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