Verification

June 9, 2020
place and route in design automated hotspot fixing

How to achieve fast, automated, sign-off verification of DFM hotspot fixes in P&R

A collaboration between GlobalFoundries and Mentor has resulted in an innovative in-design fixing strategy across markets such as IoT, mobile, RF, graphics and networking.
Article  |  Tags: , , , , , , ,   |  Organizations: ,
June 4, 2020
UVM - Universal Verification Methodology

UVM coding guidelines offer clarity in a complex world

These 13 suggestions toward best practice address some of the most persistent challenges with the Universal Verification Methodology.
June 2, 2020
Tom Anderson is a technical marketing consultant working with multiple EDA vendors, including AMIQ EDA. His previous roles have included vice president of marketing at Breker Verification Systems, vice president of applications engineering at 0-In Design Automation, vice president of engineering at IP pioneer Virtual Chips, group director of product management at Cadence, and director of technical marketing at Synopsys. He holds a Master of Science degree in Computer Science and Electrical Engineering from M.I.T. and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst.

VHDL users also deserve efficient design and verification

More commonly associated with SystemVerilog, IDEs can also greatly help users of the popular HDL for FPGA, mil/aero and other designs.
Expert Insight  |  Tags: , , ,   |  Organizations:
May 29, 2020
Dr Lauro Rizzatti is a verification consultant and industry expert on hardware emulation.

Covid-19 rings changes for virtual working

Virtualization is becoming ever more common during the Covid-19 outbreak, even for complex technologies like emulation, and showing its strengths.
Expert Insight  |  Tags: , , , ,   |  Organizations: , ,
April 21, 2020
reset domain crossing featured image

How to achieve accurate reset domain crossing verification

The authors describe an emerging methodology based on a hierarchical data model approach that satisfies the key requirements for RDC verification.
April 14, 2020
Power ground check featim

How automated power/ground short checks slash time during implementation

Early detection using design integrity checks during implementation from abstract LEF/DEF inputs can deliver major efficiencies.
Article  |  Tags: , , , , , , , , ,   |  Organizations:
March 17, 2020
FeatIm P&R MaxLinear Mentor

How MaxLinear got faster signoff DRC while optimizing reliability and manufacturability

The RF and AMS specialist turned to design software that allowed it to run design checks during place and route.
February 28, 2020
SystemVerilog logo

Make it easier to exercise state machines with SystemVerilog

How the use of declarative, constraint-based descriptions can help you focus command sequences on areas of interest.
Article  |  Tags: , , , , ,   |  Organizations: ,
February 20, 2020
Adnan Hamid is co-founder and CEO of Breker Verification Systems, and inventor of its core technology. He has more than 20 years of experience in functional verification automation and is a pioneer in bringing to market the first commercially available solution for Accellera’s Portable Stimulus Standard.

Verifying AI engines

How can we refine our approach functional verification to deal with the increasing number of systems that leverage artificial intelligence.
February 14, 2020
P2P-Feb20-featuredimage

A better way to debug P2P results

P2P (point-to-point) resistance is fundamental to IC reliability verification. Handle it more efficiently with detailed, automated path layout analysis.

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors