Verification

November 27, 2019

Managing code coverage to achieve verification closure in low-power SoCs

A look at some of the key techniques needed to ensue good code coverage during the verification of low-power SoC designs.
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November 22, 2019
Raghav Katoch is a product engineer with the Calibre physical verification team at Mentor, a Siemens business.

Improve your LVS debug productivity

A look at ways to improve LVS debug productivity on complex SoCs through more narrowly targeted debug strategies.
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November 21, 2019
Tom Anderson is a technical marketing consultant working with multiple EDA vendors, including AMIQ EDA. His previous roles have included vice president of marketing at Breker Verification Systems, vice president of applications engineering at 0-In Design Automation, vice president of engineering at IP pioneer Virtual Chips, group director of product management at Cadence, and director of technical marketing at Synopsys. He holds a Master of Science degree in Computer Science and Electrical Engineering from M.I.T. and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst.

Accelerating the adoption of portable stimulus

The vision of portable stimulus is to find a way to write tests that can be portable ‘vertically’ from IP block to subsystem to system, and ‘horizontally’ from simulation to emulation to silicon. However, applying portable stimulus to real chip designs is not trivial.
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October 16, 2019
Tom Anderson is a technical marketing consultant working with multiple EDA vendors, including AMIQ EDA. His previous roles have included vice president of marketing at Breker Verification Systems, vice president of applications engineering at 0-In Design Automation, vice president of engineering at IP pioneer Virtual Chips, group director of product management at Cadence, and director of technical marketing at Synopsys. He holds a Master of Science degree in Computer Science and Electrical Engineering from M.I.T. and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst.

Achieving the interactive development of low-power designs

Power intent files have increased efficiency and the use of an IDE can prevent them becoming outdated as a design evolves.
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October 7, 2019
Richard Pugh featured image SSD expert insight

Emulation makes it possible to stay on the road to autonomous vehicles

Autonomous vehicle functional verification needs to prove the predictable behavior, safety and security of complex SoCs and their associated software, sensors and actuators, demanding greater use of hardware emulation.
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September 12, 2019
Graphic representing alternative generation paths for PSS model

Portable stimulus and UVM

Accellera's Portable Test and Stimulus standard provides powerful features for verification that is not meant to replace UVM but augment existing verification flows. Here is how portable stimulus and UVM interact.
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September 10, 2019
Adnan Hamid is co-founder and CEO of Breker Verification Systems, and the inventor of its core technology. He has more than 20 years of experience in functional verification automation. He received his Bachelor of Science degree in Electrical Engineering and Computer Science from Princeton University, and an MBA from the University of Texas at Austin.

Using portable stimulus for automotive random error analysis

The Portable Stimulus Standard helps overcome many of the verification challenges inherent in the strict requirements of ISO 26262.
August 19, 2019
Tom Anderson is a technical marketing consultant working with multiple EDA vendors, including AMIQ EDA. His previous roles have included vice president of marketing at Breker Verification Systems, vice president of applications engineering at 0-In Design Automation, vice president of engineering at IP pioneer Virtual Chips, group director of product management at Cadence, and director of technical marketing at Synopsys. He holds a Master of Science degree in Computer Science and Electrical Engineering from M.I.T. and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst.

Take advantage of the automated refactoring of design and verification code

Refactoring saves time and resuources by converting code to a common format and eliminates redundancies to make it more readable and maintainable.
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August 9, 2019
Ashish Darbari is CEO of formal verification consultancy Axiomise.

Spreading the word on formal in Bangalore

Doc Formal rounds up some of the the key observations about verfication made during July’s Synopsys VC Formal SIG event in India.
July 23, 2019
Tom Anderson is a technical marketing consultant working with multiple EDA vendors, including AMIQ EDA. His previous roles have included vice president of marketing at Breker Verification Systems, vice president of applications engineering at 0-In Design Automation, vice president of engineering at IP pioneer Virtual Chips, group director of product management at Cadence, and director of technical marketing at Synopsys. He holds a Master of Science degree in Computer Science and Electrical Engineering from M.I.T. and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst.

Correct design and verification coding errors as you type

An IDE designed to catch typographical errors, missing declarations and inconsistent references in your code can hugely reduce your time in debug.
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