How automated power/ground short checks slash time during implementation
Early detection using design integrity checks during implementation from abstract LEF/DEF inputs can deliver major efficiencies.
DRC
Use evolving DRC to automate high-voltage and multi-power domain verification
Automated voltage-aware DRC addresses the reliability verification challenges in today’s high-voltage and multiple power domain applications.
Fast, accurate layout merging for SoC flows
How to achieve efficient merging of data from formats such as OASIS, GDS, and OpenAccess to ensure timely verification through DRC runs.
A better way to manage error reporting at the chip and block levels
In a continuous-build design flow, at which level should your error markers be addressed?
Reliability verification: It’s all about the baseline
How you can use the dedicated rule decks now being provided by foundries as the foundation for a reliability verification flow.
Managing waivers in reliability verification
Dina Medhat describes what you need to know about the types of waiver strategy that can be applied.
The three critical data validation points in a design flow
Why design data integrity matters from cell design to tapeout. These techniques will help ensure your validation process is as comprehensive as possible.
Three ways to lift productivity during physical verification
How to get the best PV results by reducing computational demands; handling data more efficiently and exploiting parallelization.
Improve custom/AMS design and productivity with in-design DRC
In-design DRC is a technique that frees up engineers from many of the challenges of delivering AMS design under ever more complex design rules.
Drawing on hierarchical DFT to benefit all designs and flows
Hierarchical DFT is vital for large, complex designs. Users still to transition to the technique can nevertheless exploit its pattern reuse strategies as they move toward adoption.
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