debug

June 13, 2017
Emulation save-and-restore debug featured image

Hardware emulation gets smarter with save-and-restore for debug

Techniques previously unavailable during ICE or testbench acceleration can now greatly speed emulation debug in those modes.
Article  |  Topics: EDA - Verification  |  Tags: , , , , ,   |  Organizations: ,
October 19, 2015
Nasib Naser is senior staff corporate applications engineer in the verification group for Synopsys.

Ten key tips for effective memory verification

Verification IP can help verify that memory-controller implementations meet standards; test an implementation against specific memories; and drive traffic for SoC verification and power analysis. Here's how to choose it.
Expert Insight  |  Topics: IP - Selection, EDA - Verification  |  Tags: , , , , ,   |  Organizations:
August 21, 2015
Visual: cars speeding along a road

Why emulation performance doesn’t matter (on its own)

Emulation performance is a key metric in verification. But it is far from being the only consideration. How long it takes to get a design onto a verification platform and aspects such as debug are as important. These factors will control how verification platforms are deployed during a project's life cycle.
August 4, 2015
Mick Posner is Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions.

Building better debug facilities for bigger FPGA-based prototypes

The introduction of bigger FPGAs enables more complex prototypes - but makes debugging more of a challenge. Here's one way to address the issue.
Expert Insight  |  Topics: EDA - Verification  |  Tags: ,   |  Organizations: ,
November 6, 2014
Dr Lauro Rizzatti is an independent verification consultant. You can contact him at lauro AT rizzatti DOT com

The budget case for emulation

Need to convince your FD of emulation’s growing ROI and the need to invest? Click here and ‘Forward’
October 15, 2014

Accelerating ‘time to prototype’ with ProtoCompiler

A look at a tool and a flow that makes it easier to put designs on to a HAPS physical prototyping system for verification, debug and software development purposes
May 24, 2014
Mick Posner is Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions.

Prototypers get faster route to first clock tick

ProtoCompiler understands HAPS FPGA prototyping hardware, so it can optimize logic placement and partitioning, even on designs with up to 250m ASIC gates.
Expert Insight  |  Topics: Embedded - Integration & Debug, EDA - Verification  |  Tags: , ,   |  Organizations:
January 27, 2014
Atrenta CDC

Spot the difference between false and real clock violations

Find how to spot some of the most common false clock-domain crossing (CDC) violations and how to efficiently find actual CDC problems that could kill a design if not corrected.
Article  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations:
December 8, 2013

Debugging with virtual prototypes – Part Two

The second part of our series illustrates VP tools and techniques using the familiar example of Linux bring-up on an ARM-based SoC.
Article  |  Topics: Embedded - Integration & Debug, EDA - Verification  |  Tags: , , ,   |  Organizations: ,
September 10, 2013

Debugging with virtual prototypes – Part One

The first in a series of articles about using virtual prototyping techniques to achieve more effective debug.
Article  |  Topics: Embedded - Integration & Debug, EDA - Verification  |  Tags: ,   |  Organizations: , , ,

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