EDA

'Design for yield' is a familiar term, but the challenges in today's increasingly large projects make a refresher on what it offers particularly timely.

ProtoCompiler understands HAPS FPGA prototyping hardware, so it can optimize logic placement and partitioning, even on designs with up to 250m ASIC gates.

Wreal modeling brings fast methods for simulating mixed-signal designs into the digital environment. And tools have arrived that make it easier to incorporate existing analog IP.

While some HW/SW co-design and verification techniques are in place, a power analysis methodology is only just emerging

The encryption chain for today's highly collaborative designs needs to be managed with care.

The configurability of processor IP such as Synopsys' ARC HS family gives designers the option to optimise for power, performance or a combination of both.

Reset is no longer simply an 'X' issue but also feeds into power optimization. Catching issues early greatly speeds verification.

Performing clock-domain crossing (CDC) checks on a flat database is difficult on complex SoCs. Hierarchy improves speed but calls for a smarter approach.

Fighter pilots have long trusted highly sophisticated automation. That’s how you can meet the challenges posed by advanced PCB design techniques.

Lithography is only just beginning to play a role in cell IP selection but early analysis already matters.