EDA

December 9, 2013
Carey Robertson is a director of product marketing at Mentor Graphics overseeing the marketing activities for layout versus schematic (LVS) and extraction products.

FinFET parasitics come under control

Extracting finFET parasitics means a shift to 3D models, field solvers for greater accuracy, and MCMM techniques.
Expert Insight  |  Topics: EDA - DFM, IC Implementation  |  Tags: , , , ,   |  Organizations:
December 8, 2013

Debugging with virtual prototypes – Part Two

The second part of our series illustrates VP tools and techniques using the familiar example of Linux bring-up on an ARM-based SoC.
Article  |  Topics: Embedded - Integration & Debug, EDA - Verification  |  Tags: , , ,   |  Organizations: ,
December 3, 2013
Dr David M Fried is Chief Technology Officer - Semiconductor at Coventor, responsible for the company’s strategic direction and implementation of its SEMulator3D Virtual Fabrication Platform.

Lithography challenges threaten the cost benefits of IC scaling

The costs of advanced lithography techniques at 1xnm, and the yield and reliability risks from the resultant process variation, will stop many companies getting the typical economic advantages of scaling.
Expert Insight  |  Topics: EDA - DFM  |  Tags: , , , , , , , , ,   |  Organizations:
November 14, 2013
Cadence virtual prototyping

A map of the prototyping ecosystem

Different users within a design team will have varying needs for prototype capabilities. What type of prototype to pick is not always 100 per cent clear. Here are some pointers on how to make the choice.
Article  |  Topics: EDA - ESL, Verification  |  Tags: , , ,   |  Organizations:
November 11, 2013
Brian Fuller is editor in chief at Cadence Design Systems.

Goodbye to the mixed-signal black box

In pursuit of better design methodologies coupled with shrinking design-cycles, real-number modeling is emerging as a smart verification choice.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations: ,
November 6, 2013

Improving performance through better delay estimation of sub-32nm interconnects

Better delay estimation of sub-32nm interconnects, in which resistivity varies up to 100x between layers, helps Cavium improve overall performance and get ready for even denser processes
November 1, 2013
Jack Erickson is director of product management at Cadence Design Systems.

Slow winter or new spring for hardware design?

Problems with process scaling make it seem as though the long era of innovative, lucrative hardware design is coming to an end. But is that really the case?
Expert Insight  |  Topics: EDA - ESL  |  Tags: , , ,   |  Organizations:
October 27, 2013
Richard Goering, senior manager of technical communications, Cadence

IPC-2581 transfer standard gains momentum

Forty six companies have joined the consortium developing the increasingly important IPC-2581 data transfer standard for PCB designs.
Expert Insight  |  Topics: PCB - System Codesign  |  Tags: ,   |  Organizations:
October 23, 2013

FPGA-based prototyping to validate the integration of IP into an SoC

A case study describing validation of the integration of USB3.0 and USB2.0 interface IP that illustrates broader challenges FPGA-based prototyping presents.
Article  |  Topics: IP - Assembly & Integration, EDA - Verification  |  Tags: , ,   |  Organizations:
October 21, 2013
Featured image for high level synthesis LP Part One

How high-level synthesis helps optimize low power designs – Part One

Going inside HLS' basics shows how it can deliver power savings over 50% for some applications.
Article  |  Topics: EDA - ESL, IC Implementation  |  Tags: ,   |  Organizations:

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