EDA

July 3, 2013
Graham Bell, RealIntent

The challenge of clock domain crossings – and some solutions

Clock domain crossing bugs undermine the productivity gains of moving to block-based design, but can be tackled through hierarchical formal analysis.
May 23, 2013
Cost of verification

Facing the verification management challenge

The growing verification challenge, and how to address it by coordinating multiple debug strategies.
May 14, 2013
Graham Bell, RealIntent

Building an RTL sign-off flow

RTL sign-off strategies ease SoC design and IP integration by enabling early analysis and optimization of CDC, power, X propagation, timing, and resetability issues.
May 8, 2013
3D-IC cross-section

Eight requirements for 3D-IC design

Many design teams are looking at ways in which they can make use of 3D integration. Here are eight requirements for an effective 3D-IC design flow.
Article  |  Topics: EDA - DFM, IC Implementation  |  Tags: , ,   |  Organizations:
May 8, 2013
Segement from PCB design rule schematic

Keeping high-speed designs clean with ERC

Electrical rule checks (ERC) are now available to deal with increasing PCB design complexity, speed project delivery and protect the intellectual property within them.
May 7, 2013
Graham Bell, RealIntent

Better analysis helps improve design quality

Better upfront analysis can help avoid propagating errors from RTL into the netlist, and reveal a number of ways to improve the quality of your final design.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:
April 30, 2013

Knock down the wall to SoC integration

SoC integration can be accelerated by using virtualization to make the benefits of emulation more accessible to both hardware and software engineers.
Article  |  Topics: Embedded Topics, Embedded - Integration & Debug  |  Tags: , , ,   |  Organizations:
April 24, 2013
Mick Posner, Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions.

IP-to-SoC prototyping demands consistency

Many problems arise during the IP-to-SoC phase of FPGA-based prototyping due to the mix-and-match nature of the prototypes not the actual designs.
Expert Insight  |  Topics: IP - Assembly & Integration, - EDA Topics, IP Topics, EDA - Verification  |  Tags: , ,   |  Organizations: ,
April 24, 2013
Colin Walls

The rush to open source tools

Mind how you go. The only truly free thing about open source tools is the download itself. There is, however, a 'third way', matching professional support to these often useful options.
Expert Insight  |  Topics: Embedded - Architecture & Design, Integration & Debug, User Experience  |  Tags: , ,   |  Organizations: ,
April 22, 2013
Layout segment showing problem of color splitting with double patterning

The five key challenges of sub-28nm custom and analog design

The arrival of the 20nm and finFET-based 14nm and 16nm processes bring with them challenges for custom IC design. These are the five key areas and a methodology that can address them.

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