EDA

Using a physically aware flow to ensure that fixing one ECO doesn't introduce another during sign off.

Shifting DFM validation earlier in the flow speeds NPI, cuts respins and gives you a critical edge.

An in-depth look at the role of FPGA-based prototyping and the validation use cases it offers when integrating complex blocks.

Decoupling capacitor counts are increasing as PCBs deploy more advanced silicon. But you can use automated analysis to bring counts and costs under control.

Verification of hardware and software has become a key bottleneck for chip design. Hardware-assisted verification is removing that bottleneck.

In a standing-room-only talk at the recent DesignCon conference, Eric Bogatin explained why comedian Henny Youngman could help them with signal integrity on PCBs.

Catching x-propagation issues at RTL saves time and reduces uncertainty in gate-level verification

Increasingly complex state machines are driving the need for smarter ways of reporting errors such as deadlocks and unreachable code in the source RTL.

Advanced tools are being applied to established nodes to produce advanced designs for volume markets.

The number of scenarios needed for MCMM timing analysis has skyrocketed. IC implementation calls for a concurrent approach to deal with the issue.