December 1, 2014
Formal techniques can be applied to various parts of the verification challenge, including low-power and clock domain-crossing issues
November 23, 2014
Emulation and simulation acceleration technologies provide the means to more efficiently detect power issues before tapeout – and find the worst-case modes that need to be fixed.
November 6, 2014
Need to convince your FD of emulation’s growing ROI and the need to invest? Click here and ‘Forward’
November 5, 2014
Fab and IP vendor collaboration is making pattern matching-based libraries a vital component of DRC accuracy and efficiency. Learn how to take advantage.
October 31, 2014
A look under the hood of IC Compiler II, Synopsys' next-generation netlist-to-GDSII implementation system.
October 28, 2014
This 'how to' guide shows how to combine the power of emerging and existing technologies for faster, more comprehensive test.
October 27, 2014
This article looks at some of the key architectural and implementation decisions Synopsys has made in developing a version of its HS series of licensable processor cores to serve the embedded Linux market
October 18, 2014
Soft blocking to prevent cell spreading and other placement-optimization techniques helped improve power and clock speed on a Cortex-M7 test chip designed by ARM and Cadence.
October 15, 2014
A look at a tool and a flow that makes it easier to put designs on to a HAPS physical prototyping system for verification, debug and software development purposes
October 10, 2014
FInFET memories have different defects than those based on planar transistors. Here's how to test and repair them.