EDA

January 28, 2014
Mark Bollar is a product marketing director at Synopsys overseeing physical implementation.

Are advanced designs only possible at emerging process nodes?

Advanced design isn’t restricted to emerging process nodes any more. Designers are using the latest tools to produce advanced designs on established nodes.
January 27, 2014
Atrenta CDC

Spot the difference between false and real clock violations

Find how to spot some of the most common false clock-domain crossing (CDC) violations and how to efficiently find actual CDC problems that could kill a design if not corrected.
Article  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations:
January 21, 2014
Cadence Palladium cluster

Productivity, predictability and versatility drive verification environments

Three key characteristics determine a verification platform's ability to add value to the design flow. But how they score within a project depend on how each is applied and at which point.
Article  |  Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:
January 20, 2014
Jean-Marie Brunet is the Product Marketing Director for DFM at Mentor Graphics

Patterning choices loom for 10nm and beyond

It is not just a choice between EUV and multiple patterning for future nodes, but even between varieties of multi-mask technologies. How will you decide?
January 15, 2014
Featured image for Debugging with VPs - III

Debugging with virtual prototypes – Part Three

This part illustrates the technique using examples addressing memory corruption, multicore systems and cache coherency with particular reference to watchpoints.
January 13, 2014
Formal verification aids RTL verification

Formal verification enables Agile RTL development

Agile development started in the software domain but the methodology shows promise for SoC verification. Formal verification techniques can help implement an Agile flow.
Article  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations:
January 13, 2014
Steffen Schulze is director of marketing for Calibre Mask Data Preparation at Mentor Graphics

Consider your options for future nodes

If EUV is further delayed until 8nm, the industry has to explore other options for patterning, and the effects they will have on the DFM flow.
January 7, 2014
Neil Songcuan is a senior product marketing manager, responsible for the FPGA-based Prototyping Solution at Synopsys.

Using HAPS to streamline IP to SoC integration

The HAPS prototyping system can help designers integrate IP into SoCs more quickly.
Expert Insight  |  Topics: IP - Assembly & Integration, EDA - IC Implementation  |  Tags: , ,   |  Organizations:
December 16, 2013
Mick Posner is Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions.

Consistency key to gaining the advantages of IP integration

Consistency is vital to IP integration strategies that rely on developing an SoC using a hierarchy of FPGA-based prototypes.
December 16, 2013

How high-level synthesis helps optimize low power designs – Part Two

Continuing our series on high-level synthesis (HLS) for low power design. Part Two details how HLS helps you make and evaluate architectural decisions.

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