EDA

May 17, 2014
Real-number modeling signal resolution function

Real datatypes and tools enable fast mixed-signal simulation

Wreal modeling brings fast methods for simulating mixed-signal designs into the digital environment. And tools have arrived that make it easier to incorporate existing analog IP.
Article  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations:
May 15, 2014
Bill Neifert is chief technology officer of Carbon Design Systems. Bill has designed high-performance verification and system integration solutions, and also developed an architecture and coding style for high-performance RTL simulation in C/C++.

Bringing true power analysis to hardware/software co-design

While some HW/SW co-design and verification techniques are in place, a power analysis methodology is only just emerging
April 28, 2014

Protecting IP in a collaborative signoff environment

The encryption chain for today's highly collaborative designs needs to be managed with care.
April 28, 2014

Overcoming the power/performance paradox in processor IP

The configurability of processor IP such as Synopsys' ARC HS family gives designers the option to optimise for power, performance or a combination of both.
Article  |  Topics: IP - Selection  |  Tags: , ,   |  Organizations:
April 16, 2014
Pranav Ashar

Reset optimization pays big dividends before simulation

Reset is no longer simply an 'X' issue but also feeds into power optimization. Catching issues early greatly speeds verification.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations:
April 16, 2014
Real Intent hierarchical CDC

Hierarchy provides a smarter approach to SoC CDC verification

Performing clock-domain crossing (CDC) checks on a flat database is difficult on complex SoCs. Hierarchy improves speed but calls for a smarter approach.
Article  |  Topics: EDA - Verification  |  Tags: ,   |  Organizations:
April 8, 2014
Randall Myers is an Xpedition Flow technical marketing engineer at Mentor Graphics

Straighten up and fly right

Fighter pilots have long trusted highly sophisticated automation. That’s how you can meet the challenges posed by advanced PCB design techniques.
April 3, 2014
Joe Kwan is the Product Marketing Manager for Calibre LFD and Calibre DFM Services at Mentor Graphics.

Standard cell IP must pass the litho-friendly routing test

Lithography is only just beginning to play a role in cell IP selection but early analysis already matters.
March 27, 2014
Achieving multi-scenario signoff more quickly and predictably using timing-driven ECO

Achieving multi-scenario signoff quickly and predictably using timing-driven ECO

Using a physically aware flow to ensure that fixing one ECO doesn't introduce another during sign off.
Article  |  Topics: EDA - IC Implementation  |  Tags: , , , ,   |  Organizations:
March 27, 2014
Julian Coates is the director of business development for Mentor Graphics Valor division.

Make best-practice lean NPI for PCB a reality

Shifting DFM validation earlier in the flow speeds NPI, cuts respins and gives you a critical edge.
Expert Insight  |  Topics: PCB Topics, PCB - System Codesign  |  Tags: , , , ,   |  Organizations:

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