May 17, 2014
Wreal modeling brings fast methods for simulating mixed-signal designs into the digital environment. And tools have arrived that make it easier to incorporate existing analog IP.
May 15, 2014
While some HW/SW co-design and verification techniques are in place, a power analysis methodology is only just emerging
April 28, 2014
The encryption chain for today's highly collaborative designs needs to be managed with care.
April 28, 2014
The configurability of processor IP such as Synopsys' ARC HS family gives designers the option to optimise for power, performance or a combination of both.
April 16, 2014
Reset is no longer simply an 'X' issue but also feeds into power optimization. Catching issues early greatly speeds verification.
April 16, 2014
Performing clock-domain crossing (CDC) checks on a flat database is difficult on complex SoCs. Hierarchy improves speed but calls for a smarter approach.
April 8, 2014
Fighter pilots have long trusted highly sophisticated automation. That’s how you can meet the challenges posed by advanced PCB design techniques.
April 3, 2014
Lithography is only just beginning to play a role in cell IP selection but early analysis already matters.
March 27, 2014
Using a physically aware flow to ensure that fixing one ECO doesn't introduce another during sign off.
March 27, 2014
Shifting DFM validation earlier in the flow speeds NPI, cuts respins and gives you a critical edge.