Zeroing in on the problems of fast board-level interconnect
A panel session at DAC 2014 focused on the problems of high-speed, board-level interconnect and the roles of codesign and power integrity in solving them.
EDA
How the right DFY flow enhances performance and profit
'Design for yield' is a familiar term, but the challenges in today's increasingly large projects make a refresher on what it offers particularly timely.
Prototypers get faster route to first clock tick
ProtoCompiler understands HAPS FPGA prototyping hardware, so it can optimize logic placement and partitioning, even on designs with up to 250m ASIC gates.
Real datatypes and tools enable fast mixed-signal simulation
Wreal modeling brings fast methods for simulating mixed-signal designs into the digital environment. And tools have arrived that make it easier to incorporate existing analog IP.
Bringing true power analysis to hardware/software co-design
While some HW/SW co-design and verification techniques are in place, a power analysis methodology is only just emerging
Protecting IP in a collaborative signoff environment
The encryption chain for today's highly collaborative designs needs to be managed with care.
Overcoming the power/performance paradox in processor IP
The configurability of processor IP such as Synopsys' ARC HS family gives designers the option to optimise for power, performance or a combination of both.
Reset optimization pays big dividends before simulation
Reset is no longer simply an 'X' issue but also feeds into power optimization. Catching issues early greatly speeds verification.
Hierarchy provides a smarter approach to SoC CDC verification
Performing clock-domain crossing (CDC) checks on a flat database is difficult on complex SoCs. Hierarchy improves speed but calls for a smarter approach.
Straighten up and fly right
Fighter pilots have long trusted highly sophisticated automation. That’s how you can meet the challenges posed by advanced PCB design techniques.