The world of ATPG just changed with the introduction of a new way to create and choose the most effective test patterns.
An IDE is critical to top quality refactoring. Here are some tips and examples of how to achieve that.
Parasitic extraction has to take more account of inductive effects as operating frequencies rise and feature sizes shrink in complex SoCs.
SEMICON West showed a distinct thematic shift away from preserving Moore's Law to assessing the architectural implications of AI, as EDA was brought into the event.
Gandharv Bhatara looks at how the OPC and RET elements of Calibre are getting ready for the EUV age.
Insights from research into reliability at Imec led to self-learning chips, security technologies, and finFET biosensors.
3D integration technology has split into a number of different approaches, each of which brings a different combination of benefits in terms of performance.
Why is formal verification not getting the traction it should. The good doctor has some thoughts on that... and a new solution.
Our new columnist introduces himself and traces the progress of formal verification over the last two decades. Join the discussion.
Precise curved geometries are vital to making this emerging and cost-effective CMOS-based technology work. This primer explains its advantages and how litho tools are evolving to meet the challenges it presents.
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