SRAM IP “halves dynamic power” on 28nm FDSOI

By Luke Collins |  No Comments  |  Posted: June 5, 2015
Topics/Categories: Blog - IP  |  Tags: , ,  | Organizations:

sureCore has released a silicon-proven embedded SRAM IP block, for use on 28nm FDSOI processes, which it claims offers greater than 50% dynamic power savings, compared to current offerings. Static power reduction is said to be up to 35%, at a cost of a 10% area increase.

The single-port SRAM operates from  0.7-1.2V.

Guillaume d’Eyssautier, SureCore’s chairman, said: “Because of migration costs, there is still considerable innovation happening at relatively mature production nodes. These nodes are predicted to have extended longevity and strategically we felt it important to provide groundbreaking solutions for these nodes.”

The embedded memory blocks are expected to be used in ICs for wearable electronics, the Internet of Things, networking and even automotive applications, where power consumption and/or heat dissipation is an issue.

sureCore says it is working on 40nm and 28nm bulk CMOS SRAM cores for delivery later this year.

Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors